SOMP: Service-Oriented Multi Processors

et al. 2015

IEEE Trans. Comput.

Self Cite

Multi-processor system on chip (MPSoC) has been widely applied in embedded systems in the past decades. However, it has posed great challenges to efficiently design and implement a rapid prototype for diverse applications due to heterogeneous instruction set architectures (ISA), programming interfaces and software tool chains. In order to solve the problem, this paper proposes a novel high level architecture support for automatic out-of-order (OoO) task execution on FPGA based heterogeneous MPSoCs. The architecture support is composed of a hierarchical middleware with an automatic task level OoO parallel execution engine. Incorporated with a hierarchical OoO layer model, the middleware is able to identify the parallel regions and generate the sources codes automatically. Besides, a runtime middleware Task-Scoreboarding analyzes the inter-task data dependencies and automatically schedules and dispatches the tasks with parameter renaming techniques. The middleware has been verified by the prototype built on FPGA platform. Examples and a JPEG case study demonstrate that our model can largely ease the burden of programmers as well as uncover the task level parallelism.

Section: Prototype and Resultsmentioning

confidence: 99%

Architecture Support for Task Out-of-Order Execution in MPSoCs

Wang¹,

Li²,

et al. 2015

IEEE Trans. Comput.

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“…Since the IP cores can be configured with custom execution cycles in hardware, they can play the same role with the remaining benchmarks to demonstrate the effectiveness of the MP-Tomasulo approach. Furthermore, the hardware implementation of the platform is detailed in the referenced SOMP [Wang et al 2011] architecture.…”

Section: Platform Setupmentioning

confidence: 99%

MP-Tomasulo

Wang

ACM Trans. Archit. Code Optim.

et al. 2013

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This article presents MP-Tomasulo, a dependency-aware automatic parallel task execution engine for sequential programs. Applying the instruction-level Tomasulo algorithm to MPSoC environments, MPTomasulo detects and eliminates Write-After-Write (WAW) and Write-After-Read (WAR) inter-task dependencies in the dataflow execution, therefore to operate out-of-order task execution on heterogeneous units. We implemented the prototype system within a single FPGA. Experimental results on EEMBC applications demonstrate that MP-Tomasulo can execute the tasks out-of-order to achieve as high as 93.6% to 97.6% of ideal peak speedup. A comparative study against a state-of-the-art dataflow execution scheme is illustrated with a classic JPEG application. The promising results show MP-Tomasulo enables programmers to uncover more task-level parallelism on heterogeneous systems, as well as to ease the burden of programmers. ACM Reference Format:Wang, C., Li, X., Zhang, J., Zhou, X., and Nie, X. 2013. MP-Tomasulo: A dependency-aware automatic parallel execution engine for sequential programs.

“…In order to address the above challenges, servicesoriented architecture (SOA) have been demonstrated as an effective method to improve programmability and scalabil-ity [3]. However, this study is immature that we explored further contributions in this paper in the following aspects: 1) Although [3] was implemented in FPGA, it does not involve automatic reconfigurable characteristics into a sound architecture design.…”

Section: Introductionmentioning

confidence: 99%

“…However, this study is immature that we explored further contributions in this paper in the following aspects: 1) Although [3] was implemented in FPGA, it does not involve automatic reconfigurable characteristics into a sound architecture design. In this paper, we integrate a dynamic partial reconfigurable task execution model on the basis on the state-of-the-art Xilinx EAPR design methodologies and high level programming paradigms.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS

Wang

22nd International Conference on Field Programmable Logic and Applications (FPL)

et al. 2012

Self Cite

Service-oriented architecture (SOA) has been proved as an efficient way for high level programming paradigms. This paper realizes services into reconfigurable MPSoC to organize CaaS: a core as a service framework, which implements hardware services on state-of-the-art reconfigurable multi-processor system-on-chip (MPSoC) platform for high level parallelization. The integration of SOA concepts can provide structural programming models to ease the burden of high level programming. For demonstration, a prototype with JPEG application has been built on an FPGA, regarding embedded processors and IP cores as computing servants. The experimental results demonstrate the CaaS can achieve high flexibility with dynamic reconfigurable techniques.