Architecture Support for Task Out-of-Order Execution in MPSoCs

Wang, Chao; Li, Xi; Zhang, Junneng; Chen, Peng; Chen, Tianshi; Zhou, Xuehai; Cheung, Ray C. C.

doi:10.1109/tc.2014.2315628

Cited by 24 publications

(10 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2 shows the application framework for our accelerator. The accelerators are components of an application system for Deep learning applications or services as computing resources [8] [9]. Every compute node is a physical machine which includes CPU, FPGA, networking and memory.…”

Section: Architecturementioning

confidence: 99%

A Deep Learning Prediction Process Accelerator Based FPGA

Wang

et al. 2015

2015 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing

Self Cite

View full text Add to dashboard Cite

Recently, machine learning is widely used in applications and cloud services. And as the emerging field of machine learning, deep learning shows excellent ability in solving complex learning problems. To give users better experience, high performance implementations of deep learning applications seem very important. As a common means to accelerate algorithms, FPGA has high performance, low power consumption, small size and other characteristics. So we use FPGA to design a deep learning accelerator, the accelerator focuses on the implementation of the prediction process, data access optimization and pipeline structure. Compared with Core 2 CPU 2.3GHz, our accelerator can achieve promising result.

show abstract

Section: Architecturementioning

confidence: 99%

A Deep Learning Prediction Process Accelerator Based FPGA

Wang

et al. 2015

2015 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing

Self Cite

View full text Add to dashboard Cite

show abstract

“…Kshitij Sudan reduces page size to enhance memory access efficiency in [19]. Works to reduce the DRMA latency are also carried out in [2], [12], [14], [15], [16], [18]. But all of these researches treat Kernel's accesses and User's accesses equally.…”

Section: Related Workmentioning

confidence: 99%

Kernel-User Space Separation in DRAM Memory

Sun

Zhu

et al. 2014

2014 IEEE International Symposium on Parallel and Distributed Processing With Applications

Self Cite

View full text Add to dashboard Cite

Performance of software is increasingly restricted by the Memory Wall instead of CPU. Many studies focus on alleviating the DRAM latency by improving the row-buffer hit rate. But most of them treat the Kernel 1 and User 2 equally. Data used by Operating System and User applications spread in different rows of the same bank, leading to the contentions for the row-buffer when they access the bank successively. We find that contentions between Kernel and User make up of a great proportion of all the row-buffer misses. To alleviate the contentions between Kernel and User, we divide the united DRAM memory space into Kernel-Space and User-Space. A new page-allocation-system, the K/U-Aware page-allocation-system, is proposed to manage Kernel-Space and User-Space in DRAM memory in different address mapping schemes of DRAM memory controller. In the new system, pages are allocated from different spaces according to applicants (Kernel or User). Sizes of the two spaces increase and decrease dynamically as required. For benchmarks in PARSEC suites, the proposed system reduces the contentions of Kernel and User effectively, producing significant improvements of row-buffer hit rate. The execution time is reduced by 9.45% (max. 20.45%) and 6.51% (max. 18.05%) respectively in two typical address mapping schemes.

show abstract

“…These complex embedded architectures feature various timing requirements as well as differing levels of security [4], [5], [6], [7]. These design requirements lead to a trend of applying a combination of different processors, hardware Intellectual Property (IP) blocks and shared memory resources into a heterogeneous multiprocessor system-on-chip (MPSoC) to accommodate the increasing complexity of the applications [8], [9], [10]. These flexible systems, which provide hardware and software programmability, are adaptable, reusable, easy to upgrade and get to market faster, thus maximising the value of the end-product.…”

Section: Introductionmentioning

confidence: 99%

Pro-Active Policing and Policy Enforcement Architecture for Securing MPSoCs

Siddiqui

Hagan

Sezer

2018

2018 31st IEEE International System-on-Chip Conference (SOCC)

View full text Add to dashboard Cite

Embedded multiprocessor system-on-chip (MPSoC) architectures allow implementation of mixed critical applications and provide security mechanisms to segregate and protect system resources such as ARM TrustZone. These architectures enforce strict security measures right from the powering on of the system, to prevent misuse and compromise. However, such security measures have been found vulnerable where security design practices are not considered or are poorly implemented, particularly at software and hardware stack boundaries. Also, the embedded solutions developed using these MPSoC platforms are vulnerable to single points of failure and do not contain active response or mitigations for circumstances where a compromise occurs. This paper proposes pro-active hardware based policing and policy enforcement approach, along with system architecture and its hardware components, to this research problem. The architecture is physically isolated from the rich computing resources which actively monitors communications of system resources on the ARM AMBA-AXI4 bus. It detects anomalous system behaviours such as policy violation or compromised bus communication responses, and responds with predefined active countermeasures, such as deletion of secret data or disabling of the device to tackle security vulnerabilities and attacks at runtime. This proposed solution complements existing embedded hardware and software security technologies and provides an additional layer of hardware security when a vulnerability is found and exploited. This contribution lends itself to the principle of least privilege, implemented in software-based access control solutions like SELinux to mitigate when other protections have failed. This paper presents a proof-of-concept work supported by preliminary synthesis results on Xilinx Zynq-7000 and Ultra-Scale+ MPSoC chips.

show abstract

Architecture Support for Task Out-of-Order Execution in MPSoCs

Cited by 24 publications

References 35 publications

A Deep Learning Prediction Process Accelerator Based FPGA

A Deep Learning Prediction Process Accelerator Based FPGA

Kernel-User Space Separation in DRAM Memory

Pro-Active Policing and Policy Enforcement Architecture for Securing MPSoCs

Contact Info

Product

Resources

About