Some New Results on Average Worst Case Carry

Briley, Bruce E.

doi:10.1109/t-c.1973.223748

Cited by 22 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…en, the output carry bits of the remaining blocks are evaluated by means of the carry selection chain. e longest chain of unknown carry bits determines the time duration of the latter operation [7,8,14,15]. When all the carries are ready, the adder performs the sum selection to produce the result.…”

Section: Timing Analysis and Model Of The Variable Completion Timementioning

confidence: 99%

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Olivieri

Mastrandrea

2013

VLSI Design

View full text Add to dashboard Cite

Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

show abstract

Section: Timing Analysis and Model Of The Variable Completion Timementioning

confidence: 99%

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Olivieri

Mastrandrea

2013

VLSI Design

View full text Add to dashboard Cite

show abstract

“…This delay tends to be one of the largest in a typical computer design [3]. On the other hand, n-bit carry-completion sensing adders [4], [5], [6] which are asynchronous have average computation time of Θ(log n) [7]. Figure 1 shows a carry lookahead adder, which is an improvement of the RCA is recognized as the fastest existing adder in the sense that carries are computed in a parallel processing style.…”

Section: Introductionmentioning

confidence: 99%

Analysis of results obtained with a new proposed low area low power high speed fixed point adder

Eshtawie¹,

Hussin

Othman

2010

2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)

View full text Add to dashboard Cite

Integer addition is one of the most important operations in digital computers digital signal processing and. In fact the speed of adders affects the speed and performance of their processors. In digital signal processing, multiply and accumulate (MAC) unit plays an important role when designing digital filters. However, this role is doubled when multiplierless techniques such as distributed arithmetic (DA) are applied. In such techniques, the addition operation is the main scale when specifying some of the design parameters such as operation speed, design area, and the power consumed. This paper discusses the results obtained from the design analyzer for the proposed addition circuit together with the results obtained for the two most common adders i.e. the carry lookahead adder (CLA) and the ripple carry adder (RCA). The results obtained for the three different adders show that the proposed addition circuit has lowest area, lowest power consumption. On the other hand, the proposed adder has an operation speed higher than the RCA and a very close to the speed of the CLA.it is worth to mention here that the proposed design is based on the concept of applying a set of if-then rules. This set of rules calculates the out sum and carry in human-like way of processing.

show abstract

“…Furthermore, ω = 1 237 × 10 −12 , and the oscillations of G ν are again very small: we have G ν ≤ 5 357 × 10 −6 . In 1973, Briley [2] considered the expected length C n of the longest carry chain when an "end-around" carry (out of the most significant position and into the least significant position) can occur, as is the case with the sign-magnitude and 1s-complement representations of signed numbers. In Section 7, we shall indicate how our method can be adapted to the analysis of carry propagation with end-around carry.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Carry Propagation in Addition: An Elementary Approach

Pippenger

2002

Journal of Algorithms

View full text Add to dashboard Cite

Some New Results on Average Worst Case Carry

Cited by 22 publications

References 3 publications

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Analysis of results obtained with a new proposed low area low power high speed fixed point adder

Analysis of Carry Propagation in Addition: An Elementary Approach

Contact Info

Product

Resources

About