Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC

Abstract

-This paper describes real chip implementation issues of Network-on-Chip (NoC) and their solutions along with series of chip design examples. The solutions described in this paper cover both architectural aspects and circuit level techniques for practical chip implementation of NoC. As for architecture level solutions, topology selection, chip-aware protocol design, and On-Chip Serialization (OCS) for link area reduction are explained. For circuit level techniques, SERDES and synchronizer design, crossbar switch partial activation, and low-voltage link are presented as the foundations for power and area efficient NoC implementation. Regarding presented solutions for NoC implementation, this paper proposes memory centric NoC (MC-NoC) for homogeneous multi processor SoC (MPSoC). Flexibility and feasibility of task mapping on homogeneous

A DRAM Centric NoC Architecture and Topology Design Approach

“…However in custom topologies the response path is usually not congested. Memory centric NoC architectures with real chip implementations are provided in [22] and [23]. However in this systems there are several memories which are on-chip and the communication between cores is done through these memories.…”

Network Interface Sharing Techniques for Area Optimized NoC Architectures

“…Since the traffic pattern is shared memory dominated, we selected the H-star topology suggested in [7] for this application and placed the shared memory in the central switch, as illustrated in Fig.9-left. Peripheral switches connect processor cores and their associated private memories.The switch radix in all cases is 5.…”

“…The problem can be relieved as in [6] by infering custom-made hardware FIFOs at the cost of flexibility. Other approaches delve into the intricacies of NI design trying to reduce its complexity [7]. However, this solution can be successful only up to a certain extent, since the support for processing cores with advanced communication capabilities (e.g., multiple oustanding transactions, out-of-order completion, quality of service guarantees) requires complex NI architectures anyway.…”

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor

“…To reduce overhead of pixel loading and comparison, we implemented special purposes memory that reads out address of local maximum pixel in response to the center pixel address input of the search window. In summary, hardware features that are advantageous for the efficient SIFT computation is as follows For efficient 1-to-N and M-to-1 data transactions, interconnection among the 10 PEs and the 8 VIPS memories are provided by the Memory-Centric NoC [13][14][15]. Contribution of the Memory-Centric NoC to the power-efficient SIFT computation is reduced external memory transactions.…”

“…To the date, there is no dedicated processor implementation which provides sufficient performance for the SIFT computation with low-power consumption. This leads us to design a single chip application specific processor with power efficient features [13][14][15] and to implement robot vision system based on the implemented chip. In this work, we present highperformance vision system that consumes much less power compared to general purpose processor based vision systems.…”