2022
DOI: 10.1021/acsnano.1c05841
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Solid-Ionic Memory in a van der Waals Heterostructure

Abstract: Defect states dominate the performance of low-dimensional nanoelectronics, which deteriorate the serviceability of devices in most cases. But in recent years, some intriguing functionalities are discovered by defect engineering. In this work, we demonstrate a bifunctional memory device of a MoS2/BiFeO3/SrTiO3 van der Waals heterostructure, which can be programmed and erased by solely one kind of external stimuli (light or electrical-gate pulse) via engineering of oxygen-vacancy-based solid-ionic gating. The de… Show more

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Cited by 6 publications
(9 citation statements)
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References 66 publications
(101 reference statements)
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“…However, it should be noted that the higher gate voltage is due to the thick SiO 2 and BMN dielectric layer. [ 6 ] By optimizing the device, it will be possible to realize reading with lower voltage in the future.…”
Section: Resultsmentioning
confidence: 99%
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“…However, it should be noted that the higher gate voltage is due to the thick SiO 2 and BMN dielectric layer. [ 6 ] By optimizing the device, it will be possible to realize reading with lower voltage in the future.…”
Section: Resultsmentioning
confidence: 99%
“…In this work, however, we introduce a newly defined EQE to make this measurement accordant with the previous discussions. We combine the ΔH with the EQE by substituting Equation 1 and Equation 5 into Equation 4 and get Equation 6: (6) where E ph is the energy of a photon, t is the time taken for one hysteresis loop to sweepand C 0 is the shunt capacitance density of SiO 2 and BMN. [29] Note that the capacitance density of BMN is a lot greater than that of the MoS 2 , so the capacitance density of the double layer, calculated by…”
Section: Eqementioning
confidence: 99%
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