Highly Reliable Van Der Waals Memory Boosted by a Single 2D Charge Trap Medium

Abstract

Charge trap materials that can store carriers efficiently and controllably are desired for memory applications. Two‐dimensional (2D) materials are promising for highly compacted and reliable memory mainly due to their ease of constructing atomically uniform interfaces, however, remain unexplored as being charge trap media. Here we discover that 2D semiconducting PbI2 is an excellent charge trap material for non‐volatile memory and artificial synapses. It is simple to construct PbI2‐based charge trap devices since no complicated synthesis or additional defect manufacturing are required. As a demonstration, MoS2/PbI2 device exhibits a large memory window of 120 V, fast write speed of 5 μs, high on‐off ratio around 106, multilevel memory of over 8 distinct states, high reliability with endurance up to 104 cycles and retention over 1.2×104 seconds. We envision that PbI2 with ionic activity caused by the natively formed iodine vacancies is unique to combine with unlimited 2D materials for versatile van der Waals devices with high‐integration and multifunctionality.This article is protected by copyright. All rights reserved

Growth of millimeter-sized 2D metal iodide crystals induced by ion-specific preference at water-air interfaces

“…All of these devices demonstrate excellent photodetection performance, surpassing previous achievements (as depicted in Fig. 5g,h) 27,29,68,69 . This clearly highlights the synergistic benefits of water-air interfacial growth and water-based fabrication techniques, offering us with good material quality and superior device performance.…”

“…Water-air interfacial synthesis of PbI 2 2D layered PbI 2 with a bandgap of ~2.5 eV, has demonstrated fascinating potential in X-ray detection, memory, optoelectronics, and spintronics applications [25][26][27][28][29][30][31][32][33][34] . Figure 1a schematically depicts the waterbased synthesis and recycle process of 2D PbI 2 nanosheets.…”

Layered Wide Bandgap Semiconductor GaPS4 as a Charge‐Trapping Medium for Use in High‐Temperature Artificial Synaptic Applications

“…Additionally, the memory window ratio exceeds 68.75% when V gmax = 40 V, which is far superior to those of previously reported transition metal dichalcogenides (TMDs) and 3D memory devices, as shown in Figure 3d. [ 39–50 ] The stored charge density within MoS 2 /GaPS 4 may be calculated using the following equations: [ 51 ] $$$$\begin{equation}{{\Delta}}Q\ = \frac{{{{\Delta}}{{V}_{th}}{{C}_{ox}}}}{q}\ \end{equation}$$$$ $$$$\begin{equation}{{C}_{ox}} = \frac{{{{\varepsilon }_0} \times {{\varepsilon }_r}}}{d}\ \end{equation}$$$$ C ox and q respectively represent the capacitance of the 90 nm SiO 2 gate dielectric layer and the electron charge. Additionally, ɛ 0 of 8.854 × 10 −12 F m −1 and ɛ r of 3.9 respectively denote the vacuum permittivity and relative permittivity of SiO 2 , and d represents the thickness of the SiO 2 dielectric layer.…”

Photoelectric synapses based on all-two-dimensional ferroelectric semiconductor heterojunction

“…With the development of the information age, the next generation of electronic devices need to process the exponential growth of information [1][2][3]. The traditional computing technology based on complementary metal-oxide-semiconductor (CMOS) circuits and von Neumann architectures is facing the von Neumann bottleneck, which can not meet the demand of next generation information technology [4,5].…”