Solder Joint Reliability Prediction of Flip Chip Packages Under Shock Loading Environment

Abstract

Solder joint reliability under shock loading condition has been a concern over the years especially with constant reductions in the characteristic dimensions of the package and the solder joint. With the impeding transition to lead free solder, attention has moved from temperature cycle failure to mechanical shock failure. A method has been developed that employs a specially designed shock test board (STB) to characterize the solder joint performance as a function of board surface strain. This unique test board can be adapted to a wide range of test and boundary conditions. Using this board, a range of shock inputs is tested to establish correlation of the dynamic response and solder joint damage severity. The effects of package size, board thickness, and solder ball pitch are included in this paper to highlight the critical design factors for solder joint reliability in shock. This method can be used to characterize solder joint performance at the component level, early in development. One can also provide board strain based design limits guide system design and prevent late discovery of solder joint issues. Modal analysis based finite element models have been used to supplement understanding of the board response. The model demonstrates good correlation of the strain on the board and the stresses developed in the solder joint. The modeling data also suggested that the maximum principal stress at the solder joint face is a good failure criterion as it maps well with the actual failure locus found.

Dynamic Response of PCB Structures to Shock Loading in Reliability Tests

“…Two parameters have to be specified for each profile: the duration (in microseconds) and the amplitude (acceleration in number of g's, where g = 9.81 m/sec 2 is the acceleration due to gravity). The type of the input pulse used should depend on the use conditions to be simulated [13][14][15]. Selection of the input pulse affects the dynamic characteristics of the board response.…”

“…The models that have been employed to simulate the PCB assembly response to a shock loading are based, as a rule, on a linear approximation [15][16][17][18][19][20]. The series of studies have provided first-order estimates of the board deformations when subjected to an impact loading as well as the stress in the board-level interconnects.…”

“…The source of the experimental data presented here is a large database generated by various investigators and summarized in [3,15,31].…”

A mechanical fatigue assessment methodology to study solder joint reliability

“…Based on the relatively low deflection nature of high cycle fatigue, linear material properties were assumed [10]. In this study, the linear elastic, modal superposition method was adopted because of its computational efficiency.…”

Mechanical Modeling and Analysis of Board Level Drop Test of Electronic Package

“…It has been proposed that board strain may be used as an indicator of solder joint stress [8]. This assumption appears to hold well for these conditions when one examines the location of the highest board strains in Figure 8 with the peak joint stress in Figure 7.…”