Mechanical Modeling and Analysis of Board Level Drop Test of Electronic Package

Abstract

Solder Joint Reliability (SJR) issues caused by drop impact has received more and more attention from the industry in recent years. To assess the SJR in drop shock, electronic packages are generally surface mounted on a printed circuit board (PCB) whose oscillations subject the solder joint to alternating tensile and compressive loads. Many factors may affect solder joint performance in a drop test, such as the component position on the drop test board, the test board parameters (pad definition, solder resist opening, etc) and the shock pulse. This increases the difficulties in mechanical analysis of these events. Drop testing becomes more challenging than ever as environmentfriendly Pb-free solder material replaces Pb based solder. Pbfree solder has been noted [1] for increasing the risk in shock due to changes in elastic modulus and IMC strength. The failure mechanism of solder joint in drop test is also diverse. To understand all these phenomena, mechanical modeling and analysis is carried out in this paper. The modeling results have been calibrated through comparison with experiment results. Drop test based on the popular JEDEC (JESD22-B111, [2]) board were analyzed to understand the implication of this test to the electronic package. Several observations about the testing method are made, which aid in understanding the drop test results and observations are made as to how this test might be improved. A modeling design of experiment (DOE) was done to study the key structural parameters including solder ball height, package stiffness, package thickness, ball pattern and package dimension. These results are helpful in understanding the package and board design parameters to most impact drop test performance and allow for improved performance by design.

Drop and impact reliability investigation of BGA and LGA interconnects

“…2019) and static bending conditions (Gharaibeh and Almohammad, 2022;Gharaibeh, 2022a). Zhao and Garner (2006) used extensive finite element analysis (FEA) to examine the solder standoff height on the impact-induced interconnect solder stresses and related that to solder fatigue life computations. The numerical results of their simulations showed that the taller lead-free joints are exposed to higher stresses and, thus, shorter fatigue life.…”

“…The mechanical behavior assessment of electronic assemblies and handheld devices, like cell phones and tablets, under shock and impact has become a major goal in the past few decades. Therefore, researchers all over the globe have conducted numerous experiments, numerical and analytical research studies to properly evaluate the reliability and fatigue life behavior of electronic packages when exposed to impact loadings (Xi et al , 2015; Gharaibeh et al , 2013; Kallolimath and Zhou, 2016; Ghaffarian, 2022; Gharaibeh and Pitarresi, 2022). Besides, because of the continuous demand for thinner and more reliable devices, land grid array (LGA) interconnects are becoming an appealing and much fashionable design choice over the conventional ball grid array (BGA) solder balls (Joshi et al , 2012; Kujala et al , 2002a).…”

“…Other numerical and analytical studies of Gharaibeh and his co-workers suggested that, generally, shorter SAC305-based interconnects have improved fatigue performance, that is, reliability, in harmonic vibration (Gharaibeh et al, 2018b;Gharaibeh, 2018aGharaibeh, , 2018bGharaibeh, , 2019, random vibration (Gharaibeh, 2020;Gharaibeh and Pitarresi, 2019) and static bending conditions (Gharaibeh and Almohammad, 2022;Gharaibeh, 2022a). Zhao and Garner (2006) used extensive finite element analysis (FEA) to examine the solder standoff height on the impact-induced interconnect solder stresses and related that to solder fatigue life computations. The numerical results of their simulations showed that the taller lead-free joints are exposed to higher stresses and, thus, shorter fatigue life.…”