SOI SJ high voltage device with linear variable doping interface thin silicon layer

Abstract

A novel high concentration linear variable doping interface thin silicon layer (TSL) silicon-on-insulator (SOI) super junction (SJ) LDMOS is proposed. The design of the linear variable doping can deplete the high drift concentration. The proposed structure uses a TSL to achieve charge balance and eliminate substrate-assisted depletion effect. The dielectric electric field (E I ) and the breakdown voltage (BV) of the TSL SOI SJ are 530 V/mm and 552 V with 30 mm length drift region and 1 mm-thick dielectric layer, respectively, and the specific on-resistance (R on, sp ) is 0.03403 V . cm 2 and FOM (FOM ¼ BV 2 /R on,sp ) is 8.95 MW/cm 2 , when gate voltage is 5 V.Introduction: The SOI SJ can improve the trade-off characteristic between BV and R on,sp in a power device. But the substrate-assisted depletion (SAD) effect of SOI SJ upsets the delicate charge balance (CB) between the N and P pillars of the SOI SJ, which is the charge interaction between the SJ region and the substrate in the off-state. The charge imbalance between the pillars leads to the drop of BV in the SJ device, especially at high doping levels [1]. Since enhancing the dielectric electric field is a feasible way to increase the BV, so several new structures have been proposed by using the enhanced dielectric layer field (ENDIF) principle, in which introducing interface charges is effective and attractive [2,3]. Based on the theoretical and experimental investigations of TSL SOI [4-9], a novel SOI SJ with an interface thin silicon layer is proposed in this Letter, which provides a higher BV than the conventional SOI SJ. The influences of structure parameters on BV are analysed by ISE [10] and special on-resistance (R on,sp ) is studied.

Optimization of Lateral Superjunction Based on the Minimum Specific ON-Resistance

“…To analyze this effect, the equivalent substrate (ES) model was proposed in [1] to give the optimized substrate conditions. The superior R ON performances have been reported by both the experiments [2]- [8], [11], [14] and the simulations [9], [10], [12], [13], in which R ON values were given for the special doping points [2]- [9], [11], [14] or with the dose of 2 × 10 12 cm −2 from the reduced surface field [10], [12], [13]. Yet less attention has been paid to the analytical R ON optimization of the SJ-LDMOS based on its 3-D field distribution.…”

“…The optimization of the lateral SJ device mainly focuses on the design of V B , i.e., the suppression of the substrate-assisted depletion (SAD) effect, which can be alleviated by removing the silicon substrate [2], [8] or introducing the charge compensation [1], [3]- [7], [9]- [14]. To analyze this effect, the equivalent substrate (ES) model was proposed in [1] to give the optimized substrate conditions.…”

A 300 V thin layer SOI nLDMOS based on RESURF and MFP

“…However, thin layer SOI technology suffers from a low breakdown voltage [2,5]. In order to obtain thin layer SOI nLDMOS with BV more than 200 V, different device structures are proposed, such as ultra-thin SOI layer [7][8][9] and linear variable doped drift region [10][11][12][13]. However, the complicated manufacturing processes of those structures greatly increase the cost.…”

Robust and area-efficient nLDMOS-SCR with waffle layout structure for high-voltage ESD protection

“…Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications.Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices.…”

“…Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices.…”