Software Security and Randomization through Program Partitioning and Circuit Variation

Abstract

The commodity status of Field Programmable Gate Arrays (FPGAs) has allowed computationally intensive algorithms, such as cryptographic protocols, to take advantage of faster hardware speed while simultaneously leveraging the reconfigurability and lower cost of software. Numerous security applications have been transitioned into FPGA implementations allowing security applications to operate at real-time speeds, such as firewall and packet scanning on high speed networks. However, the utilization of FPGAs to directly secure software vulnerabilities is seemingly non-existent.Protecting program integrity and confidentiality is crucial as malicious attacks through injected code are becoming increasingly prevalent. This paper lays the foundation of continuing research in how to protect software by partitioning critical sections using reconfigurable hardware. This approach is similar to a traditional coprocessor approach to scheduling opcodes for execution on specialized hardware as opposed to running on the native processor. However, the partitioned program model enables the programmer the ability to split portions of an application to reconfigurable hardware at compile time. The fundamental underlying hypothesis is that synthesizing portions of programs onto hardware can mitigate potential software vulnerabilities. Further, this approach provides an avenue for randomization or diversity for software layout and circuit variation.

Moving target defense: state of the art and characteristics

“…Also, he believed that some automatic techniques, such as input rectification, functionality excision, functionality replacement, loop perforation, and cyclic memory allocation, can remove the superfluous functionality of a program and thus can eliminate security vulnerabilities (i.e., reduce the attack surface) while enabling the system to provide the normal service. Andel et al (2014) proposed that the protected program with known vulnerabilities would be divided into sections of invulnerable and vulnerable parts, and that the invulnerable sections would run on a traditional processor as usual while the vulnerable sections run on a field-programmable gate array (FPGA), which can make sure that the attacks on the vulnerable sections are no longer carried out. In this sense, it seems that the attack surface of the protected program is reduced.…”

The Application of Moving Target Defense to Field Programmable Gate Arrays

“…An FPGA can undergo PR and PDR without stopping execution, as long as the part being reconfigured isn't in use while the update is happening [3]. This allows FPGAs to be changed dynamically during execution, and when paired with circuit variants or program partitioning [2] allows for MTD at the circuit level. Having a partitioned program on a SoC could even be made to mimic scheduling specific parts of code to run on a co-processor for performance increases [8].…”

“…A program can be represented logically as a circuit, which also means that equivalent circuits can be created where all of the circuits will have the same functionality [2]. Combining PDR with circuit variants, and possibly program partitioning, will allow a SoC to have a dynamically, and probably constantly, changing circuitry implementation of a program without effecting the functional aspect.…”

Investigating the Applicability of a Moving Target Defense for SCADA Systems

“…Though hardware based version using a FPGA as a register might increase speed enough to be used on a machine in the control center, this is a technique still under development (Andel et al, 2014) and not yet amenable to integration into any SCADA system component.…”