Software for Multiprocessor Networks on Chip

Grammatikakis, Miltos D.; Coppola, Marcello; Sensini, F.

doi:10.1007/0-306-48727-6_14

Cited by 4 publications

(4 citation statements)

References 20 publications

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“…To increase the reuse of the control plane Software across multiple MP-SoC platform generations, the Hardware dependant Software (HdS) portions are wrapped into a stack of middleware, RTOS, and driver layers [20,24].…”

Section: Control-plane Processingmentioning

confidence: 99%

Heterogeneous MP-SoC

Kogel¹,

Meyr

2004

Proceedings of the 41st Annual Design Automation Conference

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To meet conflicting flexibility, performance and cost constraints of demanding signal processing applications, future designs in this domain will contain an increasing number of application specific programmable units combined with complex communication and memory infrastructures. Novel architecture trends like Application Specific Instruction-set Processors (ASIPs) as well as customized buses and Network-on-Chip based communication promise enormous potential for optimization. However, state-of-the-art tooling and design practice is not in a shape to take advantage of this advances in computer architecture and silicon technology. Currently, EDA industry develops two diverging strategies to cope with the design complexity of such application specific, heterogeneous MP-SoC platforms. First, the IPdriven approach emphasizes the composition of MP-SoC platforms from configurable off-the-shelf Intellectual Property blocks. On the other hand, the design-driven approach strives to take design efficiency to the required level by use of system level design methodologies and IP generation tools. In this paper, we discuss technical and economical aspects of both strategies. Based on the analysis of recent trends in computer architecture and system level design, we envision a hand-in-hand approach of signal processing platform architectures and design metholodgy to conquer the complexity crisis in emerging MP-SoC developments.

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Section: Control-plane Processingmentioning

confidence: 99%

Heterogeneous MP-SoC

Kogel¹,

Meyr

2004

Proceedings of the 41st Annual Design Automation Conference

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“…In contrast, we define the other class multiprocessor systems-on-chip (MPSoC), which contain simpler cores and many application-specific heterogeneous coprocessors, embedded memories and peripherals, and are targeted for embedded applications (multimedia, video, graphics) in tightly cost-and power-constrained markets (e.g., smart phones, home entertainment centers) [ARM11 MPCore ;SiliconHive;Cumming 2003;Richardson 2002;Ackland et al 2000;Philips Semiconductor;Grammatikakis et al 2003]. …”

Section: Introductionmentioning

confidence: 99%

Cache coherence tradeoffs in shared-memory MPSoCs

Loghi

Poncino

Benini

2006

ACM Trans. Embed. Comput. Syst.

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Shared memory is a common interprocessor communication paradigm for single-chip multiprocessor platforms. Snoop-based cache coherence is a very successful technique that provides a clean shared-memory programming abstraction in general-purpose chip multiprocessors, but there is no consensus on its usage in resource-constrained multiprocessor systems on chips (MPSoCs) for embedded applications. This work aims at providing a comparative energy and performance analysis of cache-coherence support schemes in MPSoCs. Thanks to the use of a complete multiprocessor simulation platform, which relies on accurate technology-homogeneous power models, we were able to explore different cache-coherent shared-memory communication schemes for a number of cache configurations and workloads.

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“…These systems can be classified into two broad classes: general purpose chip multiprocessors [1,2,3] (GPCMs), and Multi-Processor Systems-on-Chip (MPSoC) [4,5,6,7,8]. GPCMs are composed of a small number of advanced processor cores (e.g.…”

Section: Introductionmentioning

confidence: 99%

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors

Loghi

Letis

Benini

et al. 2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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The performance of the various cache coherence protocols proposed in the literature have been extensively analyzed in the context of high-performance multi-processor systems. A similar analysis for Multi-Processor Systems-on-Chips (MPSoCs), where energy is at least as important as performace, and for which strict constraints on hardware and software resources do exist, has not been done yet. This work provides an effort in that sense, showing energy/performance tradeoffs for different snoop-based protocols on a realistic MPSoC architecture. The analysis leverage a multiprocessor simulation platform, augmented with accurate power models, that allows cycle-accurate simulations. Our analysis show that (i) cache write policy is actually more important than the actual cache coherence protocol, and (ii) matching the programming model and style to the architecture may have dramatic effects on the energy and performance of the system.

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Software for Multiprocessor Networks on Chip

Cited by 4 publications

References 20 publications

Heterogeneous MP-SoC

Heterogeneous MP-SoC

Cache coherence tradeoffs in shared-memory MPSoCs

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors

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