Cache coherence tradeoffs in shared-memory MPSoCs

Loghi, Mirko; Poncino, Massimo; Benini, Luca

doi:10.1145/1151074.1151081

Cited by 38 publications

(20 citation statements)

References 24 publications

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“…Other designs implement cache systems with two private levels and a third shared level among all cores [6,12]. [13] compares three different approaches for ensuring cache coherence in Multiprocessor System on Chip (MPSoC) architectures, which are snoopy-based, software-based, and OSbased approaches. The comparison results of different snoop-based cache coherency schemes, reveals that these schemes have a strong sensitivity to the cache write policies more than the coherency protocol.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

El-Kustaban

Qahtan

2015

J. sci. technol.

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Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to get Chip Multiprocessor (CMP) by placing several processors on the same chip die. The CMP is the dominant architecture to improve the performance of the current computing systems. However, accessing a shared data by several processors is a primary challenge in CMP. The data consistency must be reached among all memory hierarchies to ensure correct behavior and higher performance. This paper, proposed a CMP with an efficient multilevel cache system, which enhances miss rate and latency (penalty) by designing and implementation of different write policies with two levels of cache. The proposed system is implemented and tested using Hardware Description Language (VHDL) on Altera's FPGA chip. The results show that a combination of write-through without buffer for the first level and write-back for the second level offers a clear improvement on the multilevel cache system performance.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

El-Kustaban

Qahtan

2015

J. sci. technol.

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“…The field of cache coherence has been extensively studied over the past 30 years resulting in lots of comparisons and surveys: [4][5][6][7][8][9][10]. There were numerous proposed inventions or solutions [11][12][13][14][15][16][17][18][19][20] to improve performance of shared memory multiprocessor architectures.…”

Section: Related Workmentioning

confidence: 99%

“…Some studies use cycle-accurate bit-accurate (CABA) simulators [1,6]. When comparing protocols is done with cycle-accurate models, implementing every protocol is difficult [23].…”

Section: Related Workmentioning

confidence: 99%

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

Massas

Pétrot

2010

Des Autom Embed Syst

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International audienceThis paper presents a novel simulation-based approach which targets the performance estimation of cache coherence protocol implementations. Our approach allows to model a cache coherence protocol where coherence transactions take zero cycle and do not generate communication accesses, in the hope that it will provide a close lower bound on latency and traffic. The protocol modeling approach relies on cycle-accurate simulation models in which components can access instantaneously and transparently internal states of other components. Using this strategy, the access time and the traffic due to cache misses are taken into account as it would be on a multiprocessor system without cache coherence. However, the proposed approach still ensures that processors receive coherent data. We detail the implementation of this approach in a cycle accurate multiprocessor simulation environment. To show its effectiveness, we implement cache and memory models for two coherence protocols both with and without our omniscient cache coherence (OCC) proposal. We show with a formal method that this approach makes it possible to preserve the consistency models implied by the cache coherence protocols, and experimentally that the OCC strategy protocol gives a close lower bound on latency and traffic

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“…LTHOUGH cache memory improves the overall system performance, the cache consumes significant amount of additional power [1,2]. Excessive power consumption may defeat the performance gain of multi-core embedded systems as embedded systems suffer from limited power supply (e.g.…”

Section: Introductionmentioning

confidence: 99%

On the design of low-power cache memories for homogeneous multi-core processors

Asaduzzaman

Rani

Sibai

2010

2010 International Conference on Microelectronics

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We investigate the impact of level-1 cache (CL1) parameters, level-2 cache (CL2) parameters, and cache organizations on the power consumption and performance of multi-core systems. We simulate two 4-core architectures -both with private CL1s, but one with shared CL2 and the other one with private CL2s. Simulation results with MPEG4, H.264, matrix inversion, and DFT workloads show that reductions in total power consumption and mean delay per task of up to 42% and 48%, respectively, are possible with optimized CL1s and CL2s. Total power consumption and the mean delay per task depend significantly on the applications including the code size and locality.Index Terms-Cache memory organization, homogeneous systems, low-power design, multi-core processor

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Cache coherence tradeoffs in shared-memory MPSoCs

Cited by 38 publications

References 24 publications

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

On the design of low-power cache memories for homogeneous multi-core processors

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