2020
DOI: 10.1109/access.2020.3041463
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Software-Defined Radio Transceiver Design Using FPGA-Based System-on-Chip Embedded Platform With Adaptive Digital Predistortion

Abstract: In this paper, a software-defined radio (SDR) based transceiver system is designed and implemented on the system-on-chip (SoC) platform, which consists of a high-speed Arm embedded processor and a reconfigurable field-programmable gate array (FPGA). In the proposed SDR transceiver, the real-time baseband signal generation and adaptive digital predistortion (ADPD) units are implemented on the SoC platform. Memory polynomial model based ADPD solution is implemented to linearize the radio frequency (RF) power amp… Show more

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Cited by 17 publications
(11 citation statements)
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“…From the hardware side, GPP-based SDR platforms performance can be enhanced by different solutions such as : a) increasing the processing speed of GPP host by using more number of cores (as reported by our work) with higher clock speed, memory and cache, and b) using external hardware accelerators such as GPU, FPGA and DSPs. In literature, these solutions were more or less studied theoretically (using GPU [58], [59], [103], FPGA [56], [91], [104], [105], DSPs [93], [94]) but it's still an open challenge to fully investigate experimentally. In addition, the latency due to the interface between the GPP and external should be considered.…”
Section: A Hardware and Software Optimizationsmentioning
confidence: 99%
“…From the hardware side, GPP-based SDR platforms performance can be enhanced by different solutions such as : a) increasing the processing speed of GPP host by using more number of cores (as reported by our work) with higher clock speed, memory and cache, and b) using external hardware accelerators such as GPU, FPGA and DSPs. In literature, these solutions were more or less studied theoretically (using GPU [58], [59], [103], FPGA [56], [91], [104], [105], DSPs [93], [94]) but it's still an open challenge to fully investigate experimentally. In addition, the latency due to the interface between the GPP and external should be considered.…”
Section: A Hardware and Software Optimizationsmentioning
confidence: 99%
“…Neural Network-Based Model Waveform Processing at Transmission and Observation Path [67], [81], [89]- [103] [110]- [120], [122], [123] [67], [75], [82]- [88] DAC and ADC nonidealities [29], [130], [133]- [141] RF Sub-Components Effects [130]- [132], [142], [145] [130], [131] Amplitude-Compensated Phase Shifter [78], [79], [148]- [155], [157], [158] Phase-Compensated and Low-Noise Variable Gain Amplifier [44], [149], [159]- [169] SVM-Based Model better output performance. Since the invention of wireless communication, the linearity of transmitting signals hold paramount importance [73], [74].…”
Section: Baseband Waveform Processing Volterra Series-based Modelmentioning
confidence: 99%
“…On the other hand, a software-defined radio (SDR) based TRX with FPGA utility serves as a contrary solution to alleviate high system cost and hardware integration of commercial black-box TRX drivers. Kumar et al [133] developed a DPD platform with system-on-chip (SoC) embedded SDR-based TRX. It has been shown that the real-time acquisition of PA inverse model coefficients in SDR-based TRX has a fast heuristic convergence speed than that of the commercial DPD TRXs due to the high-speed SoC embedded processors.…”
Section: • Critical Analysismentioning
confidence: 99%
“…Hence, most of SDR integrations for IoT scenarios have used the flexible radios on the gateway side where energy constraints are greatly alleviated [4]. Standalone embedded SDRs are based on SoC [5], [6] or custom multiprocessor architectures based on Network On Chips (NoC) [7]. If it allows portability and flexibility, it also leads to energy consumption several orders of magnitude higher than the requirements for IoT end-devices [8].…”
Section: Introductionmentioning
confidence: 99%