Software defined Network-on-Chip for scalable CMPs

Scionti, Alberto; Mazumdar, Somnath; Portero, Antoni

doi:10.1109/hpcsim.2016.7568323

Cited by 14 publications

(10 citation statements)

References 18 publications

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“…The minimalist set of additional instructions is also used to dynamically control the configuration of each router, thus allowing the software to define customised topologies and partition the chip resources. It is worth noting that this group of instructions have been inspired by other works [16,30,31]. Here, we provide effective implementation of the physical substrate, thus further demonstrating the benefit of mapping data-driven execution paradigm over a highly configurable massive parallel processing fabric.…”

Section: System Overviewmentioning

confidence: 59%

“…Other works, e.g., [25], is focused on the analysis of fixed hybrid topologies. In [16], the authors presented their approach to software programming of the NoC topology. Here, the physical substrate is based on a 2D-mesh network, built on top of simple rings running in both the x - and y -dimensions of the mesh.…”

Section: System Overviewmentioning

confidence: 99%

“…The partial idea of the paper is fundamentally influenced by [16]. Hierarchical organisation of the network allows for better exploitation of data and computation locality.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Scionti

Mazumdar

Portero

2018

Sensors

Self Cite

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The rapid evolution of Cloud-based services and the growing interest in deep learning (DL)-based applications is putting increasing pressure on hyperscalers and general purpose hardware designers to provide more efficient and scalable systems. Cloud-based infrastructures must consist of more energy efficient components. The evolution must take place from the core of the infrastructure (i.e., data centers (DCs)) to the edges (Edge computing) to adequately support new/future applications. Adaptability/elasticity is one of the features required to increase the performance-to-power ratios. Hardware-based mechanisms have been proposed to support system reconfiguration mostly at the processing elements level, while fewer studies have been carried out regarding scalable, modular interconnected sub-systems. In this paper, we propose a scalable Software Defined Network-on-Chip (SDNoC)-based architecture. Our solution can easily be adapted to support devices ranging from low-power computing nodes placed at the edge of the Cloud to high-performance many-core processors in the Cloud DCs, by leveraging on a modular design approach. The proposed design merges the benefits of hierarchical network-on-chip (NoC) topologies (via fusing the ring and the 2D-mesh topology), with those brought by dynamic reconfiguration (i.e., adaptation). Our proposed interconnect allows for creating different types of virtualised topologies aiming at serving different communication requirements and thus providing better resource partitioning (virtual tiles) for concurrent tasks. To further allow the software layer controlling and monitoring of the NoC subsystem, a few customised instructions supporting a data-driven program execution model (PXM) are added to the processing element’s instruction set architecture (ISA). In general, the data-driven programming and execution models are suitable for supporting the DL applications. We also introduce a mechanism to map a high-level programming language embedding concurrent execution models into the basic functionalities offered by our SDNoC for easing the programming of the proposed system. In the reported experiments, we compared our lightweight reconfigurable architecture to a conventional flattened 2D-mesh interconnection subsystem. Results show that our design provides an increment of the data traffic throughput of 9.5% and a reduction of 2.2× of the average packet latency, compared to the flattened 2D-mesh topology connecting the same number of processing elements (PEs) (up to 1024 cores). Similarly, power and resource (on FPGA devices) consumption is also low, confirming good scalability of the proposed architecture.

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Section: System Overviewmentioning

confidence: 59%

Section: System Overviewmentioning

confidence: 99%

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Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Scionti

Mazumdar

Portero

2018

Sensors

Self Cite

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“…The proposed morphing solution is flexible enough so that it can be exploited to tailor the NoC topology to the application requirements. Similarly to [47], by selectively bypassing or disabling links, it is possible to allow the NoC to assume a special (virtualised) configuration that provides more performance for the specific application. Figure 6 (right) shows the modification to the control signals to allow morphing capabilities.…”

Section: Morphing Capabilitymentioning

confidence: 99%

Ring-mesh: a scalable and high-performance approach for manycore accelerators

Mazumdar

Scionti

2019

J Supercomput

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There are increasing number of works addressing the design challenges of fast, scalable solutions for the growing number of new type of applications. Recently, many of the solutions aimed at improving processing element capabilities to speed up the execution of machine learning application domain. However, only a few works focused on the interconnection subsystem as a potential source of performance improvement. Wrapping many cores together offer excellent parallelism, but it brings other challenges (e.g., adequate interconnections). Scalable, power-aware interconnects are required to support such a growing number of processing elements, as well as modern applications. In this paper, we propose a scalable and energy efficient Network-on-Chip architecture fusing the advantages of rings as well as the 2D-mesh without using any bridge router to provide high-performance. A dynamic adaptation mechanism allows to better adapt to the application requirements. Simulation results show efficient power consumption (up to 141.3% saving for connecting 1024 cores), 2x (on average) throughput growth with better scalability (up to 1024 processing elements) compared to popular 2D-mesh while tested in multiple statistical traffic pattern scenarios.

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“…However flows, that are not managed by the SDN controller, use the XY routing algorithm. Thereafter Scionti et al [9] use the SDN architecture in order to explore dynamic changes in the network topology; each Processing Element (PE) has specific instructions to control the network topology by software, including switch off the links which are not used. Another interesting approach is proposed by Berestizshevsky et al [10], in which an SDNoC strategy by implementing a network manager is introduced, acting as controller with global view of the network, which controls the network in adaptive manner.…”

Section: Introductionmentioning

confidence: 99%

SSPSoC: A Secure SDN-Based Protocol over MPSoC

Ellinidou

Sharma

Rigas

et al. 2019

Security and Communication Networks

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In recent years, Multi-Processor System-on-Chips (MPSoCs) are widely deployed in safety-critical embedded systems. The Cloud-of-Chips (CoC) is a scalable MPSoC architecture comprised of a large number of interconnected Integrated Circuits (IC) and Processing Clusters (PC) destined for critical systems. While many researches have focused on addressing the hardware issues of MPSoCs, the communication over them has not been very well explored. Following the SDN concept, we propose a new protocol in order to secure the communication and efficiently manage the routing within the CoC. The SSPSoC includes a private key derivation phase, a group key agreement (GKA) phase, and a data exchange phase in order to ensure that basic security primitives are preserved and provide secure communication. Furthermore, a network of 1-30 nodes is set in order to validate the proposed protocol and measure the network performance and memory consumption of the proposed protocol.

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Software defined Network-on-Chip for scalable CMPs

Cited by 14 publications

References 18 publications

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Ring-mesh: a scalable and high-performance approach for manycore accelerators

SSPSoC: A Secure SDN-Based Protocol over MPSoC

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