Software-defined DVT-T2 demodulator using scalable DSP processors

Yang, Ho; Basutkar, Navneet; Xue, Peng; Kim, Kyeongyeon; Park, Young-Hwan

doi:10.1109/tce.2013.6531127

Cited by 12 publications

(2 citation statements)

References 20 publications

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“…First, DVB-T2, DVB-C2, and DVB-S2 transmission systems operate with a number of different transmission modes and parameters, which makes the receiver architecture more complex. A software (S/W)-based implementation enables one to implement complex functions easily and more rapidly than a H/W-based implementation [5]. Moreover, addition and modification of functions are easily extensible through the S/W upgrade.…”

Section: Multi-mode Broadcasting Receivermentioning

confidence: 99%

Integrated DVB-X2 Receiver Architecture with Common Acceleration Engine

Lee

Kook

2019

Applied Sciences

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This paper proposes an integrated DVB-X2 receiver architecture to support multi-mode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The entire system consists of a tuner block, a H/W-based receiver engine, a frame processor, and an A/V decoder. Specifically, an integrated architecture to solve key design and technical issues such as reducing the complexity of the receiver, efficiently accessing the H/W-based receiver engine, and simplifying an OFDM demodulator is proposed. The H/W-based receiver engine for DVB-X2 demodulation and channel decoding functions is implemented in two FPGA devices. The frame processor is implemented with 256 MB memory and a DSP operating at a clock speed of 1.0 GHz. To verify functionalities of the proposed DVB-X2 receiver, various test scenarios were considered in the laboratory setting. In particular, the proposed system was tested under various operating modes, as specified in standards such as DVB-T2, DVB-C2, and DVB-S2, and demonstrated successful operations in all test scenarios.

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Section: Multi-mode Broadcasting Receivermentioning

confidence: 99%

Integrated DVB-X2 Receiver Architecture with Common Acceleration Engine

Lee

Kook

2019

Applied Sciences

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“…Still require the enhanced performance and great flexibility based on multiple algorithms for software-defined demodulators. [8] Manohar Ayinala proposed a novel memory-based FFT architecture that computes the RFFT based on the modified radix-2 algorithm in An In-Place FFT Architecture for Real-Valued Signals. The algorithm computes only half of the output samples and removes the redundant operations from the flow graph.…”

Section: Introductionmentioning

confidence: 99%

Review on Scalable FFT Architecture for High Speed Communication Standard

2015

IJSR

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The Fast Fourier transform (FFT) has presently a key role in signal processing applications. Most of the system needs high flexibility, high speed and high efficiency. The baseband hardware should be economical and capable enough to compute FFT within the time constraints necessary to support multiple wireless standards. Baseband hardware should be scalable so it supports multiple wireless standards as well as it should meet the performance constraints such as high speed, low area and low power consumption. Hence, the baseband hardware needs a scalable FFT module that meets the performance constraints required by multiple wireless standards. This paper presents a highly efficient hierarchical design of an application specific instruction set processor architecture exploration, software tools design, system verification and design implementation. Simulation and synthesis results show that our FFT-ASIP achieves a higher energy-efficiency and flexibility and the area cost will be low.

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Design and Implementation of a Flexible Multi-Mode DVB-T/H Receiver and Extension to DVBT-2

Abdallah

2017

J Sign Process Syst

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Software-defined DVT-T2 demodulator using scalable DSP processors

Cited by 12 publications

References 20 publications

Integrated DVB-X2 Receiver Architecture with Common Acceleration Engine

Integrated DVB-X2 Receiver Architecture with Common Acceleration Engine

Review on Scalable FFT Architecture for High Speed Communication Standard

Design and Implementation of a Flexible Multi-Mode DVB-T/H Receiver and Extension to DVBT-2

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