Software-defined DVB-T2 receiver using coarse-grained reconfigurable array processors

Basutkar, Navneet; Yang, Ho; Xue, Peng; Bae, Kwang‐Hak; Park, Young-Hwan

doi:10.1109/icce.2013.6487026

Cited by 8 publications

(9 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Multi-core architecture with dynamically reconfigurable array processors [10] is more flexible than [6][7][8][9] because the shared data-memory banks are connected to all processing cores through crossbar switches unlike communication among the CGRAs is only restricted by NoC or on-chip bus in [6][7][8][9]. However the centralized shared data-memory banks may cause performance bottleneck with much power consumption when the number of cores increases.…”

Section: Related Workmentioning

confidence: 99%

“…It is because there is performance limitation with general NoC-based multi-core architecture. Another SRP-based multi-core architecture is shown in [7] -it is composed of ARM9 processor, two CGRAs, and AHB bus which couples them. Even though they have demonstrated the software implementation of DVB-T2 on dual CGRAs running at 400 MHz, this work also shows performance limitations because of inefficient resource utilization in the multi-core architecture.…”

Section: Related Workmentioning

confidence: 99%

“…However, most of them are monotonous aggregation of several CGRAs. For example, Samsung reconfigurable processor (SRP)-based multiprocessors have been presented in [6,7]. In [6], the multiprocessor consists of sixteen reconfigurable processors through networks-on-chip (NoC) interconnection with mesh type topology for exploiting data parallelism of volume rendering.…”

Section: Related Workmentioning

confidence: 99%

“…Even though they have demonstrated the software implementation of DVB-T2 on dual CGRAs running at 400 MHz, this work also shows performance limitations because of inefficient resource utilization in the multi-core architecture. In addition, power/energy evaluation of the multiprocessors are not shown in both cases [6,7].…”

Section: Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

Kim¹,

Kim

2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRAbased multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

Kim¹,

Kim

2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…This is because single CGRA is sequentially optimized for the parallelized computations in a kernel at a time whereas the overall speedup of the entire application can be achieved by kernel level parallelism (KLP). Therefore, such a limitation of single CGRA has resulted in the appearance of CGRA-based multi-core architectures [3][4][5][6][7][8][9] which allow for the multi-CGRA to support diverse KLPs. However, in the aspect of durability, there have been only a few research projects [11][12][13][14][15] for fault-tolerant CGRA without exploiting its inherent strengths as well as their works are limited to single CGRA.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Redundancy-based Fault-Recovery Scheme for Reliable CGRA-based Multi-Core Architecture

Kim¹,

Sohn²

2015

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for faultrecovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).

show abstract

Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture

Kim

Joo

Yoon

2016

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel-level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from high energy consumption and performance bottleneck when trying to exploit the KLP because of poor resource utilisation caused by insufficient flexibility. In this study, the authors propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilisation focusing on the kernel-stream type of the KLP. In addition, they introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream based on the RSF. Experimental results show that the proposed approaches improve performance by up to 88.8% and reduce energy by up to 48.2% when compared with the conventional CGRA-based multi-core architectures.

show abstract

Software-defined DVB-T2 receiver using coarse-grained reconfigurable array processors

Cited by 8 publications

References 3 publications

Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

Dynamic Redundancy-based Fault-Recovery Scheme for Reliable CGRA-based Multi-Core Architecture

Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture

Contact Info

Product

Resources

About