Software criticality analysis of COTS/SOUP

Bishop, Peter; Bloomfield, Robin; Clement, Tim; Guerra, Sofia

doi:10.1016/s0951-8320(03)00093-0

Cited by 11 publications

(9 citation statements)

References 2 publications

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“…G S = c c (g 1 + g 2 ) + c s (g 3 + g 4 + g 5 ) + c d (g 6 + g 7 ). (11) Similar to G R in (10), the values of g 1 , g 3 , g 4 , g 6 , and g 7 are always positive, and either g 2 or g 5 is (or both are) positive. Moreover, if either of g 2 or g 5 is negative, then the negative one has the lower value.…”

Section: Safety Gainmentioning

confidence: 77%

“…For example, some failures may be masked by increasing (or decreasing) H, while some other failure maskings may depend on n (or both H and n at the same time). In EMV, 6 10 } for n = {3, 4, 5, · · · , 10} respectively. This shows that as n increases, H decreases towards 1 2 following a wave shape.…”

Section: Relationships Among H P and Nmentioning

confidence: 99%

“…Software criticality is introduced in [9, 14, 6] and [7]. Based on the analysis of [6], we define "software criticality" and "software criticality to a failure" as follows. Software criticality is the software importance to safety.…”

Section: Introductionmentioning

confidence: 99%

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Improving Reliability and Safety by Trading off Software Failure Criticalities

Mendonça

Neves

2007

10th IEEE High Assurance Systems Engineering Symposium (HASE'07)

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A number of voters have been proposed for n-version programming diversity designed software systems. The knowledge about various software failure criticalities is not incorporated in the decisions of these voters. Moreover, failure classes contradict among each other with respect to their fault tolerance requirements, as a result, current voters either consider different failures equally or they mask only certain types of failures. Therefore, the voters need to consider system criticalities to different failures based on their fault tolerance requirements trade-off. We propose an approach for trading off system criticalities to different failures. In this approach, we introduce two implementation parameters: the voter constraint hardness and the number of participants in the voting process. We use failure criticalities trade-off to determine the optimal values of these two parameters. This trade-off enhances the ability of a voter to consider different failure criticalities. It also decreases the rate of performance failures. We provide an analysis for the relationships between the implementation parameters and the failure occurrence rate of each failure class. We derive system reliability and safety based on our approach, and we show gains in both of them. The proposed approach can be used to build fault tolerant systems based on n-version programming that use any generic or hybrid voter.

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Section: Safety Gainmentioning

confidence: 77%

Section: Relationships Among H P and Nmentioning

confidence: 99%

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Improving Reliability and Safety by Trading off Software Failure Criticalities

Mendonça

Neves

2007

10th IEEE High Assurance Systems Engineering Symposium (HASE'07)

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“…Criticality analysis has been extensively studied in software [29], but is quite rare in error-resilient computing device research. Only recently, the general area of criticality analysis (CA), which provides relative measures of significance for the effects of individual components on the overall correctness of system operation, has been investigated in digital circuit design.…”

Section: Related Workmentioning

confidence: 99%

Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

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confidence: 99%

Integrity Static Analysis of COTS/SOUP

Bishop

Bloomfield

Clement

et al. 2003

Lecture Notes in Computer Science

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This paper describes the integrity static analysis approach developed to support the justification of commercial off-the-shelf software (COTS) used in a safety-related system. The static analysis was part of an overall software qualification programme, which also included the work reported in our paper presented at Safecomp 2002 [1]. Integrity static analysis focuses on unsafe language constructs and "covert" flows, where one thread can affect the data or control flow of another thread. The analysis addressed two main aspects: the internal integrity of the code (especially for the more critical functions), and the intra-component integrity, checking for covert channels. The analysis process was supported by an aggregation of tools, combined and engineered to support the checks done and to scale as necessary. Integrity static analysis is feasible for industrial scale software, did not require unreasonable resources and we provide data that illustrates its contribution to the software qualification programme.

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Software criticality analysis of COTS/SOUP

Cited by 11 publications

References 2 publications

Improving Reliability and Safety by Trading off Software Failure Criticalities

Improving Reliability and Safety by Trading off Software Failure Criticalities

Optimally Fortifying Logic Reliability through Criticality Ranking

Integrity Static Analysis of COTS/SOUP

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