Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

Abstract

Testing SoC is a challenging task, bottleneck became the instruction dispatch rather than the especially when addressing complex and highinstruction execution.

A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

“…Moreover, these methods do not adequately deal with the test of the control part of the cache, despite the importance of this part for the correct behaviour of the processor. Alternatively, in [8] the authors proposed an SBST-based technique suitable for testing the controller of data cache memories. This technique does not require special features in the cache memory but relies on an accurate counter in order to validate cache memory operations.…”

“…In a few words, the exploited algorithms are based on a series of specially crafted memory access operations able to generate cache hits and misses for every data element in the cache memory, while thoroughly exciting the rest of the cache controller. In the former approach [8] the authors exploited embedded timers to determine the correctness of the executed programs; on the contrary, in this case we propose the inclusion of an I-IP to accurately and inexpensively verify whether memory accesses have been performed. In order to provide the reader with enough information about the suitability and usefulness of the presented method, the detailed approach was implemented resorting to the implementation of a SoC containing a processor core with data and instruction caches; we will also provide the reader with a feedback about the real performance of the approach detailing information about stuck-at fault coverage and test length duration, as well as about the hardware overhead required to implement the proposed I-IP.…”

“…Currently, the real challenge of software-based testing techniques is how to generate effective test programs. An SBST algorithm devoted to test the circuitry implementing the controller of caches has been proposed in [8]: this algorithm assumes that an accurate counter is available, which is exploited to check whether the expected hit or miss operations are performed by the controller. However, in some case these accurate timers could not be available or easily usable.…”

“…The stimula are internally generated by the application of some specially crafted test programs, while test responses are observed by the I-IP, which generates an error signal when an unexpected behaviour is detected. The exploited test programs are generated by flexible and parametric algorithm, previously introduced and detailed in [8] able to generate implementationindependent solutions for different cache configurations. In a few words, the exploited algorithms are based on a series of specially crafted memory access operations able to generate cache hits and misses for every data element in the cache memory, while thoroughly exciting the rest of the cache controller.…”

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches

“…Most of them propose different methodologies to adapt existing March tests [7] to cache memories, taking into account the functional and/or the RTL model [8], [9], [10], [11], [12], [13], [14], [15]. Differences in the proposed approaches mainly lay in the portion of the cache addressed by the test (e.g., [12], [13], [10], [11], [9] mainly target faults in the memory array of the cache, while [14] concentrates on its control logic). Some solutions, such as the one proposed by Sosnowski in [15], also propose the use of dedicated hardware (e.g., on-chip performance monitor) to increase the SBST test capability.…”