Soft2LM: Application Guided Heterogeneous Memory Management

Giardino, Michael; Doshi, Kshitij; Ferri, Bonnie

doi:10.1109/nas.2016.7549421

Cited by 13 publications

(14 citation statements)

References 20 publications

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“…This bandwidth can be as low as 1/10th [8] of DRAM or even lower [23], depending on the NVM technology. Hence, hybrid memory architectures utilizing a small fraction of DRAM and a large amount of NVM have been touted to be more promising which exploit the cost and capacity benefits of NVM while minimizing the disadvantages of NVM with DRAM [1,5,23].…”

Section: Nvm and Hybrid Memory Architecturesmentioning

confidence: 99%

Exploration of memory hybridization for RDD caching in Spark

Khan

Alam

Nath

et al. 2019

Proceedings of the 2019 ACM SIGPLAN International Symposium on Memory Management

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Apache Spark is a popular cluster computing framework for iterative analytics workloads due to its use of Resilient Distributed Datasets (RDDs) to cache data for in-memory processing. We have revealed that the performance of Spark RDD cache can be severely limited if its capacity falls short to the needs of the workloads. In this paper, we have explored different memory hybridization strategies to leverage emergent Non-Volatile Memory (NVM) devices for Spark's RDD cache. We have found that a simple layered hybridization approach does not offer an effective solution. Therefore, we have designed a flat hybridization scheme to leverage NVM for caching RDD blocks, along with several architectural optimizations such as dynamic memory allocation for block unrolling, asynchronous migration with preemption, and opportunistic eviction to disk. We have performed an extensive set of experiments to evaluate the performance of our proposed flat hybridization strategy and found it to be robust in handling different system and NVM characteristics. Our proposed approach uses DRAM for a fraction of the hybrid memory system and yet manages to keep the increase in execution time to be within 10% on average. Moreover, our opportunistic eviction of blocks to disk improves performance by up to 7.5% when utilized alongside the current mechanism.

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Section: Nvm and Hybrid Memory Architecturesmentioning

confidence: 99%

Exploration of memory hybridization for RDD caching in Spark

Khan

Alam

Nath

et al. 2019

Proceedings of the 2019 ACM SIGPLAN International Symposium on Memory Management

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“…Our initial performance evaluation with HPC workloads (Section 2) shows that there is 1.09x-8.4x slowdown on NVM-based systems, depending on bandwidth and latency features of NVM. Because of the limitation of NVM, NVM is often paired with a small fraction of DRAM to form a heterogeneous memory system (HMS) [1][2][3][4][5][6][7] . By selectively placing frequently-accessed data in the small amount of DRAM available in HMS, we are able to exploit the cost and scaling benefits of NVM while minimizing the limitation of NVM with DRAM.…”

Section: Introductionmentioning

confidence: 99%

Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing

2021

J. Comput. Sci. Technol.

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Non-volatile memory (NVM) provides a scalable and power-efficient solution to replace dynamic random access memory (DRAM) as main memory. However, because of the relatively high latency and low bandwidth of NVM, NVM is often paired with DRAM to build a heterogeneous memory system (HMS). As a result, data objects of the application must be carefully placed to NVM and DRAM for the best performance. In this paper, we introduce a lightweight runtime solution that automatically and transparently manages data placement on HMS without the requirement of hardware modifications and disruptive change to applications. Leveraging online profiling and performance models, the runtime solution characterizes memory access patterns associated with data objects, and minimizes unnecessary data movement. Our runtime solution effectively bridges the performance gap between NVM and DRAM. We demonstrate that using NVM to replace the majority of DRAM can be a feasible solution for future HPC systems with the assistance of a software-based data management.

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“…To make use of future main memory with NVM, several researchers have tackled to find out new system software support and memory subsystems which are appropriate for NVM characteristics [7], [8], [9]. However, no NVM-based main memories are commercially available.…”

Section: Introductionmentioning

confidence: 99%

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

Koshiba

Hirofuchi

Takano

et al. 2019

IEICE Trans. Inf. & Syst.

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Non-volatile memory (NVM) is a promising technology for low-energy and high-capacity main memory of computers. The characteristics of NVM devices, however, tend to be fundamentally different from those of DRAM (i.e., the memory device currently used for main memory), because of differences in principles of memory cells. Typically, the write latency of an NVM device such as PCM and ReRAM is much higher than its read latency. The asymmetry in read/write latencies likely affects the performance of applications significantly. For analyzing behavior of applications running on NVM-based main memory, most researchers use software-based emulation tools due to the limited number of commercial NVM products. However, these existing emulation tools are too slow to emulate a large-scale, realistic workload or too simplistic to investigate the details of application behavior on NVM with asymmetric read/write latencies. This paper therefore proposes a new NVM emulation mechanism that is not only light-weight but also aware of a read/write latency gap in NVM-based main memory. We implemented the prototype of the proposed mechanism for the Intel CPU processors of the Haswell architecture. We also evaluated its accuracy and performed case studies for practical benchmarks. The results showed that our prototype accurately emulated write-latencies of NVM-based main memory: it emulated the NVM write latencies in a range from 200 ns to 1000 ns with negligible errors from 0.2% to 1.1%. We confirmed that the use of our emulator enabled us to successfully estimate performance of practical workloads for NVM-based main memory, while an existing light-weight emulation model misestimated. key words: middleware, non-volatile memory, performance emulation, asymmetric read/write latencies, write-back awareness † The author is with Tokyo University of Agriculture and Technology, Tokyo, 184-8588 Japan.Note: this paper extends our preliminary work published at NVMSA 2017 [5]. Specifically, we reimplemented a prototype of our emulator for the Intel Haswell processors, which previously targeted for an old processor architecture (i.e., Sandy Bridge) to verify the portability of our emulator for newer processor families. Along with the reimplementation, we drastically improved the accuracy of the emulator by fixing bugs of cache miss measurement; the worst emulation error of the NVM write latency was mitigated from 28.6% to 1.1%. Moreover, we conducted thorough experiments using various workloads. All the parts of the paper are also thoroughly updated to improve the quality of the paper.

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Soft2LM: Application Guided Heterogeneous Memory Management

Cited by 13 publications

References 20 publications

Exploration of memory hybridization for RDD caching in Spark

Exploration of memory hybridization for RDD caching in Spark

Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

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