Soft error rate increase for new generations of SRAMs

Granlund, T.; Granbom, B.; Olsson, N.

doi:10.1109/tns.2003.821593

Cited by 75 publications

(31 citation statements)

References 25 publications

(35 reference statements)

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“…In [79], the neutron SER in 6T cells increased by 2x per generation from 0.25m to 0.14m. Granlund et al [80] found that the SER decreased by 2x from 0.5m to 0.25m node and then increased by 4x from 0.25m to 0.14m. This nonmonotonic trend was explained by a disproportionate scaling of Q CRIT with respect to collection efficiency.…”

Section: Neutron Ser Scalingmentioning

confidence: 98%

Characterization of soft errors caused by single event upsets in CMOS processes

Karnik

Hazucha

2004

IEEE Trans.Dependable and Secure Comput.

442

211

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Abstract-Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in highperformance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

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Section: Neutron Ser Scalingmentioning

confidence: 98%

Characterization of soft errors caused by single event upsets in CMOS processes

Karnik

Hazucha

2004

IEEE Trans.Dependable and Secure Comput.

442

211

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“…For instance, the neutron flux at 12 km (~40000 ft) altitude is around 300 times higher than at sea level and at 20 km (~60000 ft) it has its maximum peak. For this reason, integrated circuits operating at aircraft altitudes are more susceptible to faults induced by such particles than at ground level (NORMAND, 1996-b;GRANLUND;GRANBOM;OLSSON, 2003).…”

Section: A Radiation-induced Fault Modelmentioning

confidence: 99%

“…Others show the SER increase in the new technology generations of ICs due to the scaling and technology trends (HAZUCHA el al, 2003;GRANLUND;GRANBOM;OLSSON, 2003;BORKAR, 2005).…”

Section: Occurrence Rate Of Radiation-induced Effectsmentioning

confidence: 99%

Design of a soft-error robust microprocessor

Bastos¹,

Kastensmidt²,

Reis³

2009

Microelectronics Journal

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“…Soft errors in CMOS circuits occur due to charged particle strikes which are present as cosmic rays in the atmosphere and α-particles within the chip itself [1], [2], [3], [4], [5]. Soft errors in modern VLSI circuits are a major reliability concern.…”

Section: Introductionmentioning

confidence: 99%

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

Gill

Papachristou

Wolff

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Soft errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft error tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft error tolerance results are presented and compared with standard SRAM cell and an existing increased soft error tolerance cell. Simulation results show that our cell has lowest soft error rate at the various supply voltages.

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Soft error rate increase for new generations of SRAMs

Abstract: We report on enhanced susceptibility for neutron-induced soft errors from accelerated testing of static random access memories (SRAMs), performed at Los Alamos National Laboratory. This enhancement is per bit of memory.

Cited by 75 publications

References 25 publications

Characterization of soft errors caused by single event upsets in CMOS processes

Characterization of soft errors caused by single event upsets in CMOS processes

Design of a soft-error robust microprocessor

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

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