A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

Abstract

Abstract-Soft errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft error tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft error tolerance results are presented and compared with standard SRAM cell and an existing increased soft error tolerance cell. Simulation results show that our cell has lowest soft error rate at the various supply voltages.

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

“…of the new cells and all abovementioned cells. The failure rate of a cell due to particle strikes is known as the soft error rate and decreases exponentially with an increasing critical charge of the cell nodes [38]. The units of SER are Failure in Time (FIT).…”

“…The units of SER are Failure in Time (FIT). One FIT is one failure in one billion hours [38]. The following equation is generally used to calculate the FIT of a memory cell [38,39] …”

Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices

“…This will can definitely change the circuit functionality and can affect the system reliability. To overcome this issue, we employ asymmetric SRAM cell proposed in [19] that makes cells immune to soft errors when they have a specific logical value. For this purpose, we use one-optimized asymmetric cell so that the CSRAMs become immune to one-to-zero bit-flips.…”

Effect of voltage scaling on soft error protection methods for SRAMs

“…One of these models has been presented in [18], however such approach is very application specific and does not deliver complete SEU protection. Standard hardening technique is another method of SEU protection in which the physical characteristics of the transistors are increased to improve the tolerance level, Qcrit, of the cell itself.…”