Abstract-Aggressive technology scaling has resulted in stability reduction for classic SRAM designs. This is especially problematic for large integrated circuits. The stability of SRAM cells can be affected by noise during a read operation and by radiation during the standby mode. In this paper, we present an approach to address the gradual stability reduction in SRAM designs. We present an SRAM design tradeoffs approach to improve the characteristics of SRAM by modulating the transistor sizing ratio, β. We test our approach on various SRAM designs in 32nm technology. We optimize the SRAM designs with β for various constraints in power consumption, performance, radiation tolerance and data stability. We discuss different design trends produced by the extensive approach analysis.
This paper presents a novel SRAM design for nanoscale CMOS. The new design addresses the problem of low radiation tolerance and high instability for SRAM memories at feature size of 32 nm. The novelty of our approach originates from the synergetic functional component separation, where each component serves its unique operational function and has minimal effect on performance of others. The design consists of three different components: the first component is used to store the data, the second one is designed to protect the data at the most vulnerable state and last component serves to extract the data from the SRAM cell. We performed comparative analysis of our design against conventional radiation-tolerant designs in terms of power consumption, level of radiation tolerance, performance, area and stability. The benefits of our new design (high radiation tolerance, high stability, fast performance) were confirmed by extensive simulations in different 32 nm technology environments (low power, high performance, bulk).
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