Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits

Gupta, Neha; Shah, Ambika Prasad; Kumar, Rana Sagar; Raut, Gopal; Dhakad, Narendra Singh; Vishvakarma, Santosh Kumar

doi:10.1016/j.microrel.2020.114013

Cited by 6 publications

(6 citation statements)

References 25 publications

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“…The schematic of the proposed VB-ST circuit is shown in Figure 4 [3]. The bootstrap circuit is mainly helpful to improve the input impedance of the circuit, which provides better resilience to process variations.…”

Section: Proposed Vb-st Circuitmentioning

confidence: 99%

“…Also, bootstrapping is commonly useful to pull up the operating point of the transistor, which may be fruitful to achieve full voltage swing in the circuit. The main attribute of this circuit is the only use of NMOS transistors [3]. The key features of the proposed circuit are as follows: • Transistor (𝑀2) is used in the pull-up network to increase the threshold voltage and overcome the output voltage drop in the inverter circuit.…”

Section: Proposed Vb-st Circuitmentioning

confidence: 99%

“…Critical charge is estimated as the minimum amount of charge collected by the sensitive node to flip the input and output voltage. The detailed description of the critical charge estimation equation is given in [3].…”

Section: Pvt Variation On Critical Charge Analysismentioning

confidence: 99%

“…At deep submicron technology, digital circuits are highly sensitive to soft errors and the critical charge of potential striking particles. The soft error rate (SER) exponentially depends on the Q 𝑐𝑟𝑖𝑡 and it has been observed that the SER decreases when the value of Q 𝑐𝑟𝑖𝑡 increases [3]. Soft error rate is calculated for different latches as compared to the reference unhardened latch (RL) at different supply voltage and temperature conditions.…”

Section: Soft Error Rate Ratiomentioning

confidence: 99%

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Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Gupta

Amesur

Dhakad

et al. 2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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Soft error is one of the major reliability issue with technology scaling. In this work, we propose a radiation hardened voltage bootstrapped schmitt trigger (VB-ST) latch. To evaluate the circuit radiation resilience, we calculated the critical charge under the PVT variations at the most sensitive node and observed that the proposed latch has the highest critical charge and the lowest soft error rate ratio when compared to existing latches. We analyzed the impact of process variations on our design and observed that the VB-ST latch has 0.42× less critical voltage variability as compared to ST latch. Further, dynamic power and propagation delay are examined for various supply voltages, and we observed that the VB-ST latch has the lowest power consumption and delay propagation when compared to the other considered latches. For the validation of the proposed latch, a charge to power-delay-area product ratio (QPAR) is calculated and we clearly observed that the proposed VB-ST based latch significantly outperforms the performance of existing designs.

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Section: Proposed Vb-st Circuitmentioning

confidence: 99%

Section: Proposed Vb-st Circuitmentioning

confidence: 99%

Section: Pvt Variation On Critical Charge Analysismentioning

confidence: 99%

Section: Soft Error Rate Ratiomentioning

confidence: 99%

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Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Gupta

Amesur

Dhakad

et al. 2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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“…This, however, implies that the S/T has to be considered as stateful element that, inevitably, suffers from metastability [2]. Due to its wide range of application, e.g., among others for reliable circuits [3], oscillators [4] or SRAM [5], a comprehensive analysis of its Manuscript received June 12, 2021; revised October 6, 2021 and November 14, 2021; accepted November 21, 2021. The work of Jürgen Maier was supported by the Austrian Science Fund (FWF) through the Project Digital Modeling of Asynchronous Integrated Circuits (DMAC) under Grant P32431.…”

Section: Introductionmentioning

confidence: 99%

Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses

Maier

Hartl-Nesic

Steininger

2022

IEEE Trans. Circuits Syst. I

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Schmitt-Triggers (S/Ts) are often utilized to clean noisy analog signals at intermediate voltage values in digital circuits. However, they are vulnerable to metastability, which may cause the same undesired non-digital output behavior that was supposed to be removed in the first place. To enable an efficient characterization of static and dynamic metastability properties of S/Ts (e.g., the metastable voltages, the resolution time constants and the overall total resolution times), this work introduces multiple simulation approaches based on control theory, AC, DC and transient analyses. The accuracy and runtime of all methods are compared and discussed by applying them to an analytically describable idealized circuit model as well as three common circuit implementations. Altogether, this work represents a comprehensive resource for investigating the metastable behavior in S/Ts. Even more, the proposed methods are applicable beyond the S/T, enabling an efficient characterization of static and dynamic metastable behavior in general circuits as well.

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An SEU-hardened ternary SRAM design based on efficient ternary C-elements using CNTFET technology

Bakhtiary

Amirany

Moaiyeri

et al. 2023

Microelectronics Reliability

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Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits

Cited by 6 publications

References 25 publications

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses

An SEU-hardened ternary SRAM design based on efficient ternary C-elements using CNTFET technology

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