SOCRATES: a highly efficient automatic test pattern generation system

Schulz, Michael; Trischler, E.; Sarfert, T.M.

doi:10.1109/43.3140

Cited by 471 publications

(163 citation statements)

References 6 publications

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“…The TPG gradually determines a set of objectives that are necessary for activating the target fault and for propagating its effect to a primary output, while taking into account the potential effects of the other faults still in the fault list. To meet these objectives in terms of a combination of values on the primary inputs, the TPG uses similar procedure as in FAN [14] and SOCRATES [36] , but using our models (Section 2):…”

Section: System Overviewmentioning

confidence: 99%

“…This search explores the space of possible solutions using a branch-and-bound technique [15] . The convergence to a solution is improved using heuristics and techniques, described as implication and unique sensitization, that are similar to those in FAN [14] and SOCRATES [36] .…”

Section: Implication and Unique Sensitizationmentioning

confidence: 99%

“…In FAN, the backward implication procedure makes unique assignments locally from the output of each gate. In addition, global implications learned during the preprocessing phase were introduced in SOCRATES [36] The global implications help to reduce the number of backtracks and permit early recognition of conflicts and redundancies. We illustrate this learning procedure using an example.…”

Section: Implication and Unique Sensitizationmentioning

confidence: 99%

“…The method is similar to SSF TPG except that error propagation, line justification and implication consider signal ambiguity introduced by the possible presence of all faults in the circuit. The search vehicle uses techniques similar to the FAN [14] and SOCRATES [36] algorithms. Various heuristics as well as a specific fault collapsing procedure are used to reduce signal ambiguity and to find test conditions that detect a target fault.…”

Section: Introductionmentioning

confidence: 99%

“…Both local [14] and global implications [36] (learned during the preprocessing phase) are performed.…”

Section: System Overviewmentioning

confidence: 99%

See 4 more Smart Citations

On the generation of test patterns for multiple faults

1993

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This paper presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in the FAN and SOCRATES algorithms to guide the search part of the algorithm and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.

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Section: System Overviewmentioning

confidence: 99%

Section: Implication and Unique Sensitizationmentioning

confidence: 99%

Section: Implication and Unique Sensitizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Both local [14] and global implications [36] (learned during the preprocessing phase) are performed.…”

Section: System Overviewmentioning

confidence: 99%

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On the generation of test patterns for multiple faults

1993

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On invariant implication relations for removing partial circuits

1997

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Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

Shinogi¹,

Hayashi²,

Taki³

1999

Syst. Comp. Jpn.

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Pass‐transistor logic SPL has been introduced as a circuit structure to achieve lower power consumption of LSI, and its effectiveness has been confirmed. In the current study, the authors discuss a test generation method for using logic tests to detect stuck‐on faults of pass transistors in SPL. First, the authors discuss a technique for generating a logic discrepancy (D or ˜D) between a normal circuit and a faulty circuit in an SPL circuit, and a test generation procedure using this technique. Next, they discuss a technique to solve the problem of size explosion of a table, prepared in advance for this technique in order to obtain logic values in faulty circuits. Then, the authors propose DFT (design for testability) circuits featuring very low chip surface overhead and speed overhead, to improve the fault coverage. Finally, to demonstrate its effectiveness, the method was applied to benchmark circuits. © 1999 Scripta Technica, Syst Comp Jpn, 30(7): 55–68, 1999

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SOCRATES: a highly efficient automatic test pattern generation system

Cited by 471 publications

References 6 publications

On the generation of test patterns for multiple faults

On the generation of test patterns for multiple faults

On invariant implication relations for removing partial circuits

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

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