SOC test planning using virtual test access architectures

Sehgal, Anuja; Iyengar, V.; Chakrabarty, Krishnendu

doi:10.1109/tvlsi.2004.834228

Cited by 37 publications

(29 citation statements)

References 29 publications

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“…We extend the design procedure from [6] in that different clock domains can use distinct shift clock signals, which are generated inside the proposed core wrapper. This is different from the multifrequency TAM design methodologies [20], [21] proposed recently. First of all, [20] requires the tester to shift data at multiple rates.…”

Section: Wrapper Design and Optimizationmentioning

confidence: 72%

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Nicolici

Chakrabarty

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Even though many embedded cores contain several clock domains, most published methods for wrapper design have been limited to single-frequency cores. Cumbersome and invasive design techniques, such as insertion of test points, are needed to make these methods applicable to current-generation embedded cores. This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. The proposed 1500-compliant wrapper prevents clock skew and allows scan chains in different clock domains to shift test data at distinct clock frequencies, which enables a better control of power dissipation during test. We present an integer linear programming (ILP) model that can be used to minimize the core testing time under power constraints for small problem instances, and which can be combined with LP-relaxation to obtain lower bounds on the testing time for larger instances. We also present an efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances.

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Section: Wrapper Design and Optimizationmentioning

confidence: 72%

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Nicolici

Chakrabarty

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The TAT achieved by the proposed work is 11 407 cycles when S max = 32 (with S max + m ATE channels). Although the TAT is slightly higher, the proposed method applies 1120 test patterns to the cores, while the TAT in [27] is obtained for only 881 patterns. More test patterns are expected to result in higher test quality.…”

Section: ) Cachementioning

confidence: 99%

“…We also compare with the TAM optimization and test scheduling techniques mentioned in [27], which do not use compression. The best TAT reported in [27] for d695 with a TAM width of 64 b is 9869 cycles.…”

Section: ) Cachementioning

confidence: 99%

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Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.

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“…They have not addressed the issue of sizing the TAM to minimize SOC testing time. Alternative approaches that combine TAM design with test scheduling do not address the problem of wrapper design and its relationship to TAM optimization [18,19] . The GA based approach to solve the problems of test scheduling optimization for wrapper design and TAM is presented here.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Test Scheduling and Test Access for ITC-02 SOC Benchmark Circuits

Sakthivel¹

2009

Journal of Computer Science

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Problem statement:This study presented the optimized test scheduling and test access for ITC-02 SOC benchmark circuits using genetic algorithm. In the scheduling procedure of SOC, scheduling problem was formulated as a sequence of two problems and solved. Approach: Test access mechanism width was partitioned into two and three partitions and the applications of test vectors and test vector assignments for different partitions were scheduled using different operators of genetic algorithm. Results: The test application time was calculated in terms of CPU time cycles for two and three partitions of twelve ITC-02 SOC benchmark circuits and the results were compared with the integer linear programming approach. Conclusion: The results showed that the genetic algorithm based approach gives better results.

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SOC test planning using virtual test access architectures

Abstract: Recent advances in tester technology

Cited by 37 publications

References 29 publications

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Optimization of Test Scheduling and Test Access for ITC-02 SOC Benchmark Circuits

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