SoC or SoP? A balanced approach!

Davidson, E.

doi:10.1109/ectc.2001.927778

Cited by 11 publications

(3 citation statements)

References 4 publications

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“…Figure 4(c) shows a thermally enhanced flip-chip stack with a 3.7-mm-high ball grid array package with lid (not shown), with 8 W power dissipation. More recently, universities, consortia, and industry [i.e., the Fraunhofer Institute in Germany, the University of Alabama, the Association of Super-Advanced Electronic Technologies in Japan (ASET), and the Interuniversity MicroElectronics Center (IMEC)] have been reporting on emerging next-generation chip stack technology and system-in-package (SIP) or system-onpackage (SOP) products [14][15][16][17][18][19][20][21][22][23][24]. Chip stack technology research and development reports include examples of silicon through-via product opportunities and comparisons with existing wire-bond technology products.…”

Section: Figurementioning

confidence: 99%

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

et al. 2005

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System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

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Section: Figurementioning

confidence: 99%

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

et al. 2005

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“…The integration approach as described in this paper deals with IPDs and embedded passives, and as such excludes any discretes or on-chip integrated passives. Integration of RF passives with active circuitry can either be achieved monolithically or in a hybrid fashion, leading to a system-on-chip (SoC) or a system-in-a-package (SiP) solution, respectively [15,105]. The latter is often also called systemon-a-package (SoP) to make the link with SoC.…”

Section: Integration Of Rf Passivesmentioning

confidence: 99%

MEMS for wireless communications: from RF-MEMS components to RF-MEMS-SiP

Tilmans

Raedt

Beyne

2003

J. Micromech. Microeng.

219

114

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Wireless communication has led to an explosive growth of emerging consumer and military applications of radio frequency (RF), microwave and millimeter wave circuits and systems. Future personal (hand-held) and ground communications systems as well as communications satellites necessitate the use of highly integrated RF frontends, featuring small size, low weight, high performance and low cost. Continuing chip scaling has contributed to the extent that off-chip, bulky passive RF components,

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“…A n SoC solution consists of one piece of semiconductor and compromises must be made. [2] In addition, an Sip module can contain integrated passive devices, microelectromechanical devices (MEMS), antennas, and other active and passive parts. There are several challenges in Sip utilization, e.g.…”

Section: Introductionmentioning

confidence: 99%

Stacked 3-D MCP with plastic ball vertical interconnections

Miettinen

Tanskaneu²,

Ristolainen³

53rd Electronic Components and Technology Conference, 2003. Proceedings.

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Continually shrinking electronic products are incorporating more and more functionality. To ensure development in the future, new technologies are needed in semiconductors and in electronics packaging. Using 3-D packaging, devices can be made much smaller than with planar packaging. In this paper the structure and reliability of a stacked 3-D multichip package for System-in-Package (Si€') solutions is reported.The vertical connections in stacked packages play an important role. The stacked 3-D package developed utilizes solder-plated plastic halls in vertical connection between interposer Layers. The properties and reliability of these vertical interconnects are essential to the functionality of a 3-D MCP. Plastic core halls have several advantages that make them excellently suited for stacked 3-D structures, the g a p holding ability of solder-plated plastic halls is essential for fixed electrical characteristics of packages and high yield of the stacking process.Stacked 3-D MCPs with coated plastic ball vertical interconnects were manufactured to he tested. The reliability of vertical interconnects and flip chips in stacked packages against thermal stresses was studied in a -4OOC to 125°C thermal shock test.

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SoC or SoP? A balanced approach!

Cited by 11 publications

References 4 publications

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

MEMS for wireless communications: from RF-MEMS components to RF-MEMS-SiP

Stacked 3-D MCP with plastic ball vertical interconnections

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