SNEAP: A Fast and Efficient Toolchain for Mapping Large-Scale Spiking Neural Network onto NoC-based Neuromorphic Platform

Kang

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

et al. 2021

Self Cite

The liquid state machine (LSM) is a kind of spiking neural network (SNN) that usually is mapped to an NoC-based neuromorphic processor to perform tasks such as classification. The creation of these LSM models does not consider the structure of Network on Chip (NoC) which resulting in heavy communication pressure on the NoC. In this paper, we propose a hardware aware LSM network generation framework. By keeping the communication between neurons within cores as much as possible, this framework could reduce the communication overheads between cores effectively. The experimental results show that the LSM model produced by our framework could achieve state-of-art accuracy and is hardware-friendly. Compared with the mapping method, the synapses in our LSM is reduced by 94.14%, the total packets in NoC is reduced by 78.3%, the maximum transmission latency is reduced by 97.5%, the average transmission latency is reduced by 54%, the throughput increased 2.8x.

Section: Performace Analysismentioning

confidence: 99%

“…The general mapping method is to divide the LSM into multiple sub-blocks and place them in the neuron core. Currently, there are some mapping methods [4] [5] [14] to efficiently deploy SNNs or LSMs on NoC-based neuromorphic aim to improve the performance of NoC.…”

Section: Introductionmentioning

confidence: 99%

A Hardware Aware Liquid State Machine Generation Framework

Kang

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

et al. 2021

Self Cite

“…Depending on the neuron model, inputs, and synaptic strengths, networks of the same underlying structure can behave unpredictably. Because of this, algorithms like SNEAP (Li et al, 2020 ) use spike traces from simulations of the network in order to better partition based on the network activity. In this work, we chose to develop a partitioning strategy that only depends on the connectivity of the input graph.…”

Section: Introductionmentioning

confidence: 99%

“…SpiNeMap reduces the power consumption and latency for crossbar-based neuromorphic cores where the communication fabric is a single shared time-multiplexed interconnect. Previously, METIS has been used to partition spiking networks in Barchi et al ( 2018b ) and Li et al ( 2020 ). However, in the former, the cortical microcircuit network used for analysis is quite small, scaled down to only roughly 4,000 neurons and seven hundred thousand synapses.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Network Connectivity and Partitioning for Reconfigurable Large-Scale Neuromorphic Systems

et al. 2022

We present an efficient and scalable partitioning method for mapping large-scale neural network models with locally dense and globally sparse connectivity onto reconfigurable neuromorphic hardware. Scalability in computational efficiency, i.e., amount of time spent in actual computation, remains a huge challenge in very large networks. Most partitioning algorithms also struggle to address the scalability in network workloads in finding a globally optimal partition and efficiently mapping onto hardware. As communication is regarded as the most energy and time-consuming part of such distributed processing, the partitioning framework is optimized for compute-balanced, memory-efficient parallel processing targeting low-latency execution and dense synaptic storage, with minimal routing across various compute cores. We demonstrate highly scalable and efficient partitioning for connectivity-aware and hierarchical address-event routing resource-optimized mapping, significantly reducing the total communication volume recursively when compared to random balanced assignment. We showcase our results working on synthetic networks with varying degrees of sparsity factor and fan-out, small-world networks, feed-forward networks, and a hemibrain connectome reconstruction of the fruit-fly brain. The combination of our method and practical results suggest a promising path toward extending to very large-scale networks and scalable hardware-aware partitioning.

Semicond. Sci. Technol.

“…The router accepts packets from different IP cores with the help of NIs, and through links or interconnects, the packets are transferred to other routers using a routing algorithm. This is a more scalable, reusable, reliable, flexible, and secure interconnection method [5]. With technology nodes scaling beyond seven-nanometer geometry, the primary difficulties range from the integrated circuit (IC) manufacturing process, outsourced semiconductor assembly and testing, to IC substrates [6].…”

Section: Introductionmentioning

confidence: 99%

Energy consumption and performance comparison of DE optimization and PSO-based IP-core mapping technique for 2D and 3D network-on-chip

Jayshree¹,

Seetharaman²,

Pati³

2021

This work presents an intellectual property mapping challenge for networks-on-chips, namely, optimizing communications costs (CC), energy consumption (EC), and performance. To address these problems, we propose meta-heuristic two-dimensional (2D) particle swarm optimization (PSO) and three-dimensional (3D) differential evolution (DE)-based mapping techniques. The proposed mapping techniques were analyzed and compared with the various mapping techniques using various real-time benchmarks. For a better comparison of the 3D DE-based mappings, the 2D-PSO and 2D genetic algorithm (GA) approaches were then extended to 3D-PSO and 3D-GA based mapping techniques. In this work, apart from the mapping effect, the routing impact has also been examined. The Xilinx Vivado IDE 16.2 was used for synthesis, and the ZYNQ 7000 FPGA was used for the implementation of the architecture. A network simulator was used for modeling and simulation. The results obtained show that the proposed 3D DE-based mapping has high performance, low CC, and low EC.