Energy consumption and performance comparison of DE optimization and PSO-based IP-core mapping technique for 2D and 3D network-on-chip

Abstract

This work presents an intellectual property mapping challenge for networks-on-chips, namely, optimizing communications costs (CC), energy consumption (EC), and performance. To address these problems, we propose meta-heuristic two-dimensional (2D) particle swarm optimization (PSO) and three-dimensional (3D) differential evolution (DE)-based mapping techniques. The proposed mapping techniques were analyzed and compared with the various mapping techniques using various real-time benchmarks. For a better comparison of the 3D DE-based mappings, the 2D-PSO and 2D genetic algorithm (GA) approaches were then extended to 3D-PSO and 3D-GA based mapping techniques. In this work, apart from the mapping effect, the routing impact has also been examined. The Xilinx Vivado IDE 16.2 was used for synthesis, and the ZYNQ 7000 FPGA was used for the implementation of the architecture. A network simulator was used for modeling and simulation. The results obtained show that the proposed 3D DE-based mapping has high performance, low CC, and low EC.

Hybrid Optimization Algorithm Based on Double Particle Swarm in 3D NoC Mapping

“…Refs. [ 9 , 10 ] used the particle swarm algorithm to solve the mapping problem of NoCs. Simulated annealing algorithms, etc., have also been used.…”