Smoothing of Si Trench Sidewall Surface by Chemical Dry Etching  and Sacrificial Oxidation

Yahata, Akihiro; Urano, Satoshi; Inoue, Tomoki; Sügimura, Takashi

doi:10.1143/jjap.37.3954

Cited by 18 publications

(3 citation statements)

References 3 publications

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“…This phenomenon of surface smoothing has been observed in the case of thermal oxidation of silicon. [59][60][61] In fact, Yahata et al 59 have successfully utilized a similar process scheme involving sacrificial thermal oxidation of silicon followed by chemical dry etching in order to obtain very smooth silicon sidewalls having rms roughnesses less than 1 nm. A more in-depth twodimensional analysis of the thermal oxidation of silicon by Kao et al 62,63 reveals that for shorter oxidation times as is the case with the present approach, curvature effects dominate over other effects that may influence thermal oxidation ͑see Fig.…”

Section: Reactive Ion Planarization "Rip… As An Alternative To Cmpmentioning

confidence: 99%

Application of Volatility Diagrams for Low Temperature, Dry Etching, and Planarization of Copper

Kulkarni

DeHoff

2002

J. Electrochem. Soc.

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A thermodynamic analysis of the dry etching process for copper using halides is undertaken with the development of volatility diagrams. The construction of such diagrams for the Cu-Cl system is illustrated for temperatures ranging from 50 to 200°C. The copper condensed phase species and the partial pressures of the predominant copper vapor phase species are depicted on these diagrams as a function of the partial pressure of chlorine at various temperatures. From these diagrams, it is apparent that reactive ion etching (RIE) of copper based on a procedure previously utilized for aluminum, is inefficient at temperatures less than 200°C. However, closer examination of the metastable equilibrium line between condensed CuCl2 and gaseous Cu3Cl3 reveals the possibility of extremely high etch rates at low temperatures, if a reducing environment based on hydrogen is utilized for etching CuCl2. The design of a multistep, low temperature RIE process for copper, that first requires the formation of condensed CuCl2 followed by the hydrogen based etching of condensed CuCl2 (and hence copper) due to the formation of Cu3Cl3 gas, is discussed. Some important aspects for the successful implementation of this etching scheme are considered. The further utilization of this process for the purpose of reactive ion planarization of copper as a potential replacement for the problematic chemical mechanical planarization step in the damascene process, is also suggested. The role of capillarity effects in this dry planarization process is discussed briefly. © 2002 The Electrochemical Society. All rights reserved.

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Section: Reactive Ion Planarization "Rip… As An Alternative To Cmpmentioning

confidence: 99%

Application of Volatility Diagrams for Low Temperature, Dry Etching, and Planarization of Copper

Kulkarni

DeHoff

2002

J. Electrochem. Soc.

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“…This is crucial for selecting postetch treatments and designing high-performance FinFET devices. In addition to sacrificial oxidation, the sidewall roughness of the Si-fins also can be improved by the other methods, such as hydrogen annealing [24] and chemical dry etching [25].…”

Section: Roughness Measurement Of Si-fin Sidewallsmentioning

confidence: 99%

A Simple Method for Measuring Si-Fin Sidewall Roughness by AFM

Tang

Bayot

Reckinger

et al. 2009

IEEE Trans. Nanotechnology

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The gate oxide reliability and the electrical behavior of FinFETs are directly related to the surface characteristics of the fin vertical sidewalls. The surface roughness of the fin sidewalls is one of the most important structural parameters to be monitored in order to optimize the fin patterning and postetch treatments. Because of the nanometer-scale dimensions of the fins and the vertical orientation of the sidewall surface, their roughness measurement is a serious challenge. In this paper, we describe a simple and effective method for measuring the sidewall morphology of silicon fins by conventional atomic force microscopy. The present methodology has been employed to analyze fins as etched by reactive ion etching and fins repaired by sacrificial oxidation. The results show that sacrificial oxidation not only reduces the roughness of the sidewalls, but also rounds the top corners of silicon fins. The present method can also be applied to characterize sidewall roughness of other nanostructures and materials such as the polysilicon gate of transistors or nanoelectromechanical beams.Index Terms-Atomic force microscopy (AFM), FinFET, roughness of silicon fin sidewall, sacrificial oxidation.

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“…The calculated onresistance for the standard trench LDMOS is lOmR-mm', whereas the fabricated device on-resistance was 13mRmm'. The dflerence between simulated and measured onresistances is assumed to be attributed to the degraded channel mobility due to the surface roughness [4].…”

Section: Introductionmentioning

confidence: 99%

Improved 20 V lateral trench gate power MOSFETs with very low on-resistance of 7.8 mΩ·mm/sup 2/

Nakagawa

Kawaguchi²

12th International Symposium on Power Semiconductor Devices &Amp; ICs. Proceedings (Cat. No.00CH37094)

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We propose an improved lateral trench gate MOSFET with a new trench drain contact. The device is predicted to achieve 25V breakdown voltage and a very low on-resistance of 7.8 mC2*mm2, which is by 20% lower than that of previously proposed standard lateral trench gate MOSFETs. The proposed trench contact uniformly distributes the electron current in the drift layer, and effectively reduces the device on-resistance.In the present paper, we also show the detailed electrical characteristics of the fabricated standard trench gate LDMOS. The large current turn-off capability of 1 . 1~1 0~ "?was achieved by the fabricated device.

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Smoothing of Si Trench Sidewall Surface by Chemical Dry Etching and Sacrificial Oxidation

Cited by 18 publications

References 3 publications

Application of Volatility Diagrams for Low Temperature, Dry Etching, and Planarization of Copper

Application of Volatility Diagrams for Low Temperature, Dry Etching, and Planarization of Copper

A Simple Method for Measuring Si-Fin Sidewall Roughness by AFM

Improved 20 V lateral trench gate power MOSFETs with very low on-resistance of 7.8 mΩ·mm/sup 2/

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