A digital programmable retina is a functional extension of a CMOS imager, in which every pixel is fitted with a tiny digital programmable processor. We actually call it a PAR, standing for Programmable Artificial Retina. From an architectural viewpoint, a PAR is an SIMD array processor with local optical input. A PAR is aimed at processing images on-site (where they are sensed) until they can be output from the array under concentrated form. The overall goal is to get compact, fast and inexpensive vision systems, e.g. for robotics applications. PAR design is subject to harsh constraints resulting from small pixel area and sensing/processing cohabitation. Meeting these constraints leads to using peculiar architectural and circuit technique solutions. In the last three generations of PARs we have designed, semi-static shift registers have played a crucial role in the maximisation of computational power versus silicon area. In particular, the latter have been used to store, shift and -through some slight modifications -to perform local computations on images. Here, we show their abilities to support asynchronous propagation in order to implement "geodesic reconstruction", an extremely useful computational operator, in particular for image segmentation and then for object selection and manipulation purposes.
OUTLINESection 2 introduces programmable artificial retinas (PARs) in the context of CMOS imaging. Section 3 focuses on semistatic shift registers and particularly on their atomic component, the semi-static register, as most valuable building blocks in PAR design. Their progressive emergence over the last 20 years in several architectural aspects of PARs is shortly reviewed. Section 4 presents a novel semi-static-shift-register-like structure which features controllable propagation phenomena when appropriately operated. This property is to be exploited for the implementation of the so-called geodesic reconstruction operator and, more generally, to be able to address middle level vision with PARs
FROM CMOS IMAGERS TO PROGRAMMABLE ARTIFICIAL RETINASWhile pixel dimensions in focal plane arrays (FPAs) remain lowerbounded to a few microns because of hard optical limitations, CMOS transistor size keeps on decreasing in the so-called deep submicron range. Thus the continuing advances in VLSI technology will allow to lodge more and more transistors in the pixel -a few today, a few tens tomorrowwithout significantly affecting sensing performances (array size, fill factor, noise...). Concurrent progress in thin film deposition, micro-optics and 3-D integration can only accelerate this evolution.CMOS imagers are presently taking advantage of the new deal on the consumer market. A few transistors in each pixel are indeed enough to amplify the phototransduced signal in order to transfer it off the array through analog buses shared by rows of pixels. Image quality of CMOS imagers now matches that of low-end CCDs.However, there is more to do with MOS transistors in the focal plane: they may be used to format or to proc...
