A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging

An ultra‐linear CMOS image sensor for a high‐accuracy imaging system

“…Generally, APSs are placed in the pixel array, and their signals are readout by column‐level readout circuits. Source follower (SF) is the most popular readout circuit that has been widely presented in several publications . 3T‐APS is shown in Figure which employs SF as a voltage buffer.…”

Architecture and design of a programmable 3D-integrated cellular processor array for image processing

“…Apart from significant performance gains, the benefit of this approach is the elimination of data-transfer bottleneck thus increasing systems throughput. The architecture of such devices is typically based on a SIMD cellular processor arrays (CPA), with either linear processor-per-column architecture for line-by-line processing [3,4] or fine-grain processor-per-pixel implementation [5,6]. Many Processing cell is distributed across 2 layers.…”

A high speed programmable focal-plane SIMD vision chip

“…This offers the opportunity to increase quality of imaging in terms of resolution, noise for example by integrating specific processing functions such as correlated double sampling [12], anti blooming [13], high dynamic range [14], and even all basic camera functions (color processing functions, color correction, white balance adjustment, gamma correction) onto the same camera-on-chip [15]. Furthermore, employing a processing element per pixel offers the ability to exploit the high speed imaging capabilities of the CMOS technology by achieving massively parallel computations [16][17][18][19][20][21][22]. Komuro et al [16] describe a new vision chip architecture for high-speed target tracking based on hardware implementation of bit-serial and cumulative summation circuits.…”

“…Rodriguez-Vasquez et al [17,18] present a chip based on arrays of mixed-signal processing elements conceived to cover the early stages of the visual processing D. Ginhac (&) Á J. Dubois Á B. Heyrman Á M. Paindavoine LE2I-Université de Bourgogne, Aile des Sciences de l'Ingénieur, BP 47870, 21078 Dijon Cedex, France e-mail: dginhac@u-bourgogne.fr path in a fully-parallel manner. Lindgren et al [19] presents a multiresolution general-purpose high-speed machine vision sensor with on-chip image processing capabilities dedicated to high-speed multisense imaging. Sugiyama et al [20] have developed a specific imager performing both target tracking within a 512 9 512-pixel entire image area and acquisition of partial images simultaneously and independently.…”