Smart Capture Modules for Direct Sensor-to-FPGA Interfaces

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Direct Interface Circuits (DICs) carry out resistive sensor readings using a resistance-to-time-to-digital conversion without the need for analog-to-digital converters. The main advantage of this approach is the simplicity involved in designing a DIC, which only requires some additional resistors and a capacitor in order to perform the conversion. The main drawback is the time needed for this conversion, which is given by the sum of up to three capacitor charge times and their associated discharge times. This article presents a modification of the most widely used estimation method in a resistive DIC, which is known as the Two-Point Calibration Method (TPCM), in which a single additional programmable digital device pin in the DIC and one extra measurement in each discharge cycle, made without slowing down the cycle, allow charge times to be reduced more than 20-fold to values around 2 µs. The new method designed to achieve this reduction only penalizes relative errors with a small increase of between 0.2% and 0.3% for most values in the tested resistance range.

Section: Resultsmentioning

confidence: 99%

Reducing Measurement Time in Direct Interface Circuits for Resistive Sensor Readout

Hidalgo-López

Sánchez-Durán

Oballe-Peinado

2020

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“…For this, the methodology proposed in Section 3 with Q = 500 will be followed. Table 1 shows the results for uncertainty obtained with the eight resistors used, where the indications proposed in [ 36 ] have been followed to design the capture module.…”

Section: Resultsmentioning

confidence: 99%

“…Two sets of tests are performed for each resistor, 500 measurements with the remaining resistors in the column with minimum values and another 500 with the resistors with maximum values. A linear adjustment is carried out from these 8000 measures [ 36 ]. Therefore, coefficients A and B of Equation (4) are obtained.…”

Section: Resultsmentioning

confidence: 99%

“…A calibration solution which takes into account RB i resistances, and uses a single calibration resistor is proposed in [ 36 ]. The method consists on using off-time calibration (outside of the normal operation of the sensor) where, by using different resistors and measuring their discharge time, a relationship can be established between R ij and R cj .…”

Section: Description Of Architecture and Operation Modementioning

confidence: 99%

See 1 more Smart Citation

Accuracy and Resolution Analysis of a Direct Resistive Sensor Array to FPGA Interface

Oballe-Peinado

Vidal‐Verdú

Sánchez-Durán

et al. 2016

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Resistive sensor arrays are formed by a large number of individual sensors which are distributed in different ways. This paper proposes a direct connection between an FPGA and a resistive array distributed in M rows and N columns, without the need of analog-to-digital converters to obtain resistance values in the sensor and where the conditioning circuit is reduced to the use of a capacitor in each of the columns of the matrix. The circuit allows parallel measurements of the N resistors which form each of the rows of the array, eliminating the resistive crosstalk which is typical of these circuits. This is achieved by an addressing technique which does not require external elements to the FPGA. Although the typical resistive crosstalk between resistors which are measured simultaneously is eliminated, other elements that have an impact on the measurement of discharge times appear in the proposed architecture and, therefore, affect the uncertainty in resistance value measurements; these elements need to be studied. Finally, the performance of different calibration techniques is assessed experimentally on a discrete resistor array, obtaining for a new model of calibration, a maximum relative error of 0.066% in a range of resistor values which correspond to a tactile sensor.

“…A series of highly parallelized image processing devices have been made available to engineers at a very affordable price. Such devices have been widely used in various signal processing and communication systems for their significant advantages in terms of running-cost, embeddability, power consumption or flexibility [ 1 , 2 , 3 , 4 , 5 , 6 , 7 ]. For example, Zeng Yonghong [ 7 ] presented an efficient Intellectual Property (IP) core design methodology to implement a real-time image processing application, such as the Normalized Product correlation (NProd) image matching algorithm; Chiesi et al [ 2 ] proposed a new non-conventional technique based on Fuzzy Deconvolution for Scattering Center Detection (F-SCD) and its embedded implementation for real-time deployment in an automotive collision avoidance application.…”

Section: Introductionmentioning

confidence: 99%

Embedded Implementation of VHR Satellite Image Segmentation

Balla-Arabé

Ginhac

et al. 2016

Processing and analysis of Very High Resolution (VHR) satellite images provide a mass of crucial information, which can be used for urban planning, security issues or environmental monitoring. However, they are computationally expensive and, thus, time consuming, while some of the applications, such as natural disaster monitoring and prevention, require high efficiency performance. Fortunately, parallel computing techniques and embedded systems have made great progress in recent years, and a series of massively parallel image processing devices, such as digital signal processors or Field Programmable Gate Arrays (FPGAs), have been made available to engineers at a very convenient price and demonstrate significant advantages in terms of running-cost, embeddability, power consumption flexibility, etc. In this work, we designed a texture region segmentation method for very high resolution satellite images by using the level set algorithm and the multi-kernel theory in a high-abstraction C environment and realize its register-transfer level implementation with the help of a new proposed high-level synthesis-based design flow. The evaluation experiments demonstrate that the proposed design can produce high quality image segmentation with a significant running-cost advantage.