2011
DOI: 10.1109/lmwc.2011.2138686
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Small- and Large-Signal Performance of III-Nitride RF Switches With Hybrid Fast/Slow Gate Design

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Cited by 7 publications
(8 citation statements)
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“…In HFETs, when the gate bias is below the threshold voltage, the 2D channel remains undepleted in the gate-source and gate-drain regions. Figure 4 (after [6]) shows the HFET equivalent capacitances and the locations of the 2Dchannel regions. As seen, the C OFF includes three main components: gate -2D channel partial capacitances C GS , C GD and the inter-electrode capacitance C DS .…”
Section: Lcl Design Principles For Microwave Devicesmentioning
confidence: 99%
See 1 more Smart Citation
“…In HFETs, when the gate bias is below the threshold voltage, the 2D channel remains undepleted in the gate-source and gate-drain regions. Figure 4 (after [6]) shows the HFET equivalent capacitances and the locations of the 2Dchannel regions. As seen, the C OFF includes three main components: gate -2D channel partial capacitances C GS , C GD and the inter-electrode capacitance C DS .…”
Section: Lcl Design Principles For Microwave Devicesmentioning
confidence: 99%
“…Insertion loss and isolation as a function of frequency for conventional HFET and LCL based HFET ©IEEE 2011 (after[6]). …”
mentioning
confidence: 99%
“…Qualitative surface potential profiles in conventional (black line) and LCL (red line) HFETs. [3,4] Figure 10 schematically shows how the LCL concept was applied to microwave switches resulting in reduced parasitic gate-to-source and gate-to-drain capacitances in the off state and, therefore, enabling a higher isolation in the off-state and low losses in the on state [5]. The key design parameter is the RC time constant of the LCL.…”
Section: Low Conducting Layer (Lcl) Passivation For Microwave Devicesmentioning
confidence: 99%
“…
We report on several key innovations to enable high performance/high reliability of nitride based FETs that include (1) the use of Perforated Channel (PC) design; (2) surface application of Low Conducting Layers (LCLs); (3) the combination of these two approaches (for achieving the ultimate power performance at the highest switching frequencies with minimum losses); (4) novel device geometries (combining the best features of lateral and vertical devices for normally-off transistors); (5) improved control of self-heating and better heat dissipation. We also review our recent results exploring the PC channel and LCL designs [1][2][3][4][5][6]. Experimental and simulation results reported in [1-6] demonstrated a sharp increase in the breakdown voltage, a large enhancement of the cutoff frequency, a better device stability and smaller spreading of the device parameters for higher yield, improved manufacturability, and smaller self-heating due to a lower thermal impedance.
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mentioning
confidence: 99%
“…One path will typically be enabled with a high voltage, while the other is enabled with a low voltage. The most important parameters to consider when selecting an SPDT are the return loss on each port, the insertion loss from the input to each of the output ports and the isolation between the output ports [26].…”
Section: Switchesmentioning
confidence: 99%