Slip-free processing of 300 mm silicon batch wafers

Abstract

Articles you may be interested inTheoretical calculation of the acoustic force on a patterned silicon wafer during megasonic cleaning Under gravitational and thermal constraints of integrated-circuit ͑IC͒ process technology, 300-mm-diam silicon wafers can deform via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the upper yield point of the silicon material. The material attributes, such as oxygen content and the state of oxygen aggregation, are taken into account. The theoretical approach allows the calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. Plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design. Deformation due to gravitational forces can be prevented through appropriate equipment design. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulation of ''what if?'' experiments, and initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.

Peculiarities of a Defect Generation During a Heat Treatment of Large Diameter Dislocation−free Silicon Wafers With Specified Distribution of Oxygen−containing Gettering Centres

“…Известны и другие способы крепления пластин: использование четырех симметрично расположенных опор и раз-мещение пластин на кольцевых опорах. В работе [7] в одномерном приближении проведены оценки максимальных сдвиговых напряжений в пластинах кремния диаметром 200 и 300 мм, обусловленных действием гравитационных сил, для перечисленных выше способов крепления пластин.…”

Development of a linear temperature ramp-based automated system for furnace oxidation of semiconductor wafers

“…The quality of oxide layer depends upon various factors like oxidation ambient, heating and cooling ramp rate etc. At temperatures higher than 750°C, the wafer becomes plastic in nature (Fischer et al, 2000). It has already been observed that the oxide charge generation in metal-oxide-semiconductor (MOS) devices significantly depend on the ramp up/down rate, experienced by the wafer (Ueno, 1998).…”

Thermal slip sources at the extremity and bevel edge of silicon wafers

“…Under certain thermal treatments, slip can be introduced into silicon from the wafer's edge, and slip bands may extend across a significant fraction of the wafer. Slip bands have been observed by Fischer et al (2000), using Lang X-ray topography, to run in orthogonal h011i directions from near the edges of 300 mm wafers, and significant work has been done to model the stresses associated with the weight of these largediameter wafers (Bullis, 2000). There is some ambiguity in the literature as to whether the presence of slip has a major impact on device yield.…”