SLIM (TM), High Density Wafer Level Fan-Out Package Development with Submicron RDL

Kim, YoungRae; Bae, JaeHun; Chang, MinHwa; Jo, AhRa; Kim, Ji Hyun; Park, SangEun; Hiner, David; Kelly, Michaël G.; Do, WonChul

doi:10.1109/ectc.2017.334

Cited by 21 publications

(2 citation statements)

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“…There was an issue of filler drop in grinding, and thus, fine filler EMC was adopted. Selecting a suitable Developed an ultra-thin PoP using FOWLP processes Several approaches could be adopted to reduce the warpage Hsieh and Tsai (2016) Performed silicon etching after back-grinding of wafers Conducted grinding of copper tall pillars and the molded wafer to obtain the specified package height Kim et al (2017b) Embedded thin dies stacked at the wafer level…”

Section: Research Studiesmentioning

confidence: 99%

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Recent advances and applications of abrasive processes for microelectronics fabrications

Zhong

2019

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Purpose This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications. Design/methodology/approach More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs). Findings Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding. Originality/value This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

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Section: Research Studiesmentioning

confidence: 99%

“…The bulk silicon had to be removed from an interposer wafer, to adopt an ultra-thin RDL from the interposer wafer. Kim et al (2017b) performed silicon etching after back-grinding of wafers. They also conducted grinding of copper tall pillars and the molded wafer to obtain the specified package height.…”

Section: Investigated the Strengths Of Thin Fowlpsmentioning

confidence: 99%