Module floorplanning/placement considering boundary constraints is practical and crucial in modern designs because designers may want to place some I/O involved modules along the chip boundary to minimize both chip area and off-chip connections. In this paper, a boundary information checking algorithm based on a general structure representation, called Generalized Polish Expression (GPE), is proposed. The algorithm, coupled with efficient perturbations in GPE, effectively produces solutions that satisfy both the boundary constraints and small chip area requirement. The experimental results have shown good performance from our approach on several commonly used MCNC benchmarks.