Slicing floorplan design with boundary-constrained modules

Abstract

We consider in this paper the problem of slicing floorplan design with boundary-constrained modules. We develop a quadratic-time method that correctly transforms a slicing floorplan into one that satisfies all given boundary constraints. The transformation method is incorporated into our floorplanning algorithm which employs the simulated annealing technique to seek for a possibly best solution. Unlike any other existing algorithm such as the one in [10], our floorplanning algorithm is always able to generate solutions satisfying all given boundary constraints. Furthermore, the experimental results indicate that our floorplanning algorithm can also generate solutions with smaller area and interconnect wirelength than the algorithm in [10].

VLSI floorplanning with boundary constraints using generalized polish expression

“…Heuristics were used to transform a sliceable floorplan into one that satisfies the given constraints. Later, Liu et al (2001) developed a quadratic-time method to do the transformation. For the non-sliceable structures with handling boundary constraints, Lai et al (2001) explored the feasibility conditions for SP with boundary constraints and provided a feasible transformation in each perturbation.…”