VLSI floorplanning with boundary constraints using generalized polish expression

Abstract

Module floorplanning/placement considering boundary constraints is practical and crucial in modern designs because designers may want to place some I/O involved modules along the chip boundary to minimize both chip area and off-chip connections. In this paper, a boundary information checking algorithm based on a general structure representation, called Generalized Polish Expression (GPE), is proposed. The algorithm, coupled with efficient perturbations in GPE, effectively produces solutions that satisfy both the boundary constraints and small chip area requirement. The experimental results have shown good performance from our approach on several commonly used MCNC benchmarks.

A bottom up approach for placement and compaction of standard modules in VLSI circuit

“…From bottom up point of view the slicing trees describes how pairs of smaller rectangles can be combined recursively to yield larger rectangles. In this it is necessary to create a recursive process which combines together supermodules, as well as basic modules, adding together their placements in a bottom up fashion [13]. The algorithm is implemented in MATLAB environment on a PC with Intel core 2 Duo 1.8 GHZ CPU and 2 GB RAM.…”