Slack Matching Asynchronous Designs

Beerel, Peter A.; Lines, Andrew; Davies, Mike E.; Kim, Nam Hoon

doi:10.1109/async.2006.26

Cited by 61 publications

(56 citation statements)

References 17 publications

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“…Methods presented by Beerel et al [2], Prakash et al [20], and Smirnov et al [1] remove bottlenecks by strategically adding buffer stages to the circuit. These approaches, however, focus only on buffer insertion (i.e., "slack matching") and do not target other micro-architectural transformations in concert with the addition of buffers.…”

Section: A Previous Workmentioning

confidence: 99%

Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems

Gill

Singh

2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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Abstract-This paper presents a systematic approach for microarchitectural exploration in pipelined asynchronous systems, with the goal of achieving a specified throughput target while minimizing a given cost function (based on energy, area, etc.). The method includes a general framework that (i) allows for a rich extensible set of microarchitectural transformations for improving throughput; and (ii) can handle a variety of cost functions, such as area, energy, Eτ 2 and the energy-area product. In general, the space of transformations that can be applied to a given circuit is potentially infinite because an arbitrarily long sequence of transformations may be applicable. To compound the challenge, the value of the given cost function can change non-monotonically as successive transformations are applied (e.g., some transformations increase area, while others decrease area), thereby making it difficult to apply a typical branch-and-bound approach to prune the search space. Our method employs simple but effective heuristic search strategies (including greedy, lookahead, and breadth-first). A key contribution is to identify commutativity of certain transformations, thereby pruning the design space significantly. The approach was automated and applied to a number of examples. Various throughput targets were assumed: from 50% to 20x throughput improvement. In each example, the approach was successful in meeting the throughput target.

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Section: A Previous Workmentioning

confidence: 99%

Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems

Gill

Singh

2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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“…Kim and Beerel [32] go a step further and consider where to insert delays in such pipelines-an operation similar to retiming. Prakash and Martin [33] and Beerel et al [34] consider how much buffering to add to systems for maximum throughput; however, again, they do not consider systems with choice.…”

Section: Pipeline Performance Analysismentioning

confidence: 99%

Synthesis and Optimization of Pipelined Packet Processors

Soviani

Hadzic²,

Edwards

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches.

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“…For performance, works have addressed the slack matching [19] problems for both unconditional (choicefree) and conditional circuits. Unconditional circuits, like synchronous circuits, can be re-timed by buffer insertion.…”

Section: Related Workmentioning

confidence: 99%

De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits

Mamaghani

Garside

Edwards

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Asynchronous VLSI programming provides a flexible abstract formalism for concurrent systems but the is an issue for industrial adoption. The asynchronous design paradigm provides 'elasticity' enabling the system to tolerate delays in communication and computation but can impose a prohibitive communication overhead when applied at a fine-grained level. This paper proposes 'De-elastisation' in a CAD flow for asynchronous dataflow networks to improve the circuits' performance and area. To preserve the architectural advantages of asynchronous design (e.g. short cycles), circuits are classified into blocking and non-blocking loops which the De-elastisation scheme relies upon. The technique is incorporated in the Teak CAD flow. Experimental results on substantial case studies show significant performance and area improvements. This work shows 3× improvement for the first category of circuits, suitable for iterative realisations and DSP-like architectures and 4× for the second category which are suitable for concurrent realisations.

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Slack Matching Asynchronous Designs

Cited by 61 publications

References 17 publications

Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems

Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems

Synthesis and Optimization of Pipelined Packet Processors

De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits

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