SJ-FINFET: A New Low Voltage Lateral Superjunction MOSFET

Ōnishi, Yasuhiko; Wang, H.; Xu, H.P.E.; Ng, Wai Tung; Wu, Renbiao; Sin, J.K.O.

doi:10.1109/ispsd.2008.4538910

Cited by 19 publications

(16 citation statements)

References 3 publications

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“…For the conventional SJ LDMOS, the p-type and n-type pillars are usually formed in the width direction, while the photo etching precision limits the junction depth and doping concentration of SJ pillars, which increases R on,sp . The SJ FINFET in [16] has the highest FOM but with low BV and complex process. However, the N-top layer and P-buried layer of JITR LDMOS are implemented in the longitudinal direction with simpler manufacturing process.…”

Section: Resultsmentioning

confidence: 99%

“…Multiple RESURF LDMOS contains vertical structures which have multiple horizontal p-type pillars but without additional n-type pillars. For conventional SJ LDMOS [9]- [16], n-type pillars and p-type pillars are usually alternatively formed at the surface of drift region in the width direction. Further, the reported SJ LDMOS typically has high R on,sp and added masks.…”

Section: Introductionmentioning

confidence: 99%

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A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Qiao

Zhou

et al. 2014

IEEE Electron Device Lett.

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A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R on,sp ) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R on,sp and high BV of above 730 V are achieved by the JITR LDMOS. R on,sp of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV 2 /R on,sp ) in comparison to the published SJ LDMOS. Index Terms-Junction-isolated triple RESURF (JITR) LDMOS, n-type top (N-top) layer, breakdown voltage (BV), specific on-resistance (R on,sp ).

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Qiao

Zhou

et al. 2014

IEEE Electron Device Lett.

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“…This is as a result of the minimum pillar width in the SJ drift region which becomes similar to the built-in depletion region. On-resistance of the minimum pillar width cannot be further reduced and design variations of the SJ transistor are thus very limited [3,4].…”

Section: Introductionmentioning

confidence: 99%

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

Adenekan

Holland

Kálna

2018

Microelectronics Journal

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The design and optimisation of a non-planar super-junction (SJ) Si MOS-FET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (R on,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p-SJ drift region pillar width of 0.3 µm with a trench depth of 2.7 µm achieves specific on-resistance (R on,sp) of 0.21 mΩ.cm 2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in R on,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.

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“…This effect upsets the delicate charge balance between the N and P pillars of SJ, resulting in the decrease of the BV. Some new structures have been reported to eliminate the substrate-assisted depletion effect [2]- [6]. Aside from this, realizing high voltage on a thin buried oxide layer (BOX) in SOI has been a major issue, considering that the low vertical BV restricts the breakdown behavior of SOI devices.…”

Section: Introductionmentioning

confidence: 99%

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

Wang

Zhang

et al. 2009

IEEE Electron Device Lett.

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A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the highdensity oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to 6 × 10 6 V/cm, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 μm and drift length of 15 μm on a thin SOI substrate.

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SJ-FINFET: A New Low Voltage Lateral Superjunction MOSFET

Cited by 19 publications

References 3 publications

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

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SJ-FINFET: A New Low Voltage Lateral Superjunction MOSFET

Cited by 19 publications

References 3 publications

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

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Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications