Sizing Analogue Integrated Circuits by Integer Encoding and NSGA-II

Sanabria-Borbón, Adriana C.; Tlelo‐Cuautle, Esteban

doi:10.1080/02564602.2016.1276869

Cited by 10 publications

(5 citation statements)

References 16 publications

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“…Metaheuristics are a good option in the sizing of analog ICs [28][29][30]. One can handle constraints to guide the optimization algorithm to find feasible solutions and also one can identify sets of MOS transistors having the same sizes or scaled values in order to reduce the search spaces of the design variables [18], and to ensure robustness when performing PVT variation analysis [28].…”

Section: Problem Formulation and Handling Of Constraintsmentioning

confidence: 99%

“…The netlist of the OTAs is generated according to SPICE, and the design variables W and L are encoded by integer numbers, as already shown in [18]. An additional design variable is the bias current that is labeled as I B in the two OTAs shown in Figure 2 between 10 µA and 100 µA.…”

Section: Sizing Otas By Pso and Mol To Improve Dcop Conditionsmentioning

confidence: 99%

“…In this paper we show the application of PSO and MOL with the proper encoding of the design variables to evaluate the objective function that is associated to the gain-bandwidth product (GBW). The sizes of the MOS transistors are encoded by integer numbers to perform the genetic operations, and afterwards the design variables are replaced by real numbers to evaluate the electrical characteristics within SPICE [18]. Our main contribution is oriented to handle constraints within PSO and MOL during the sizing of a CMOS OTA, through the inclusion of a procedure to evaluate the DCOP conditions of each MOS transistor in each individual in the population.…”

Section: Introductionmentioning

confidence: 99%

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Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

2020

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The sizes of the metal-oxide-semiconductor (MOS) transistors in an operational amplifier must guarantee strong direct current operating point (DCOP) conditions. This paper shows the usefulness of two population-based optimization algorithms to size transistors, namely—particle swarm optimization (PSO) and many optimizing liaisons (MOL). Both optimization algorithms link the circuit simulator SPICE to measure electrical characteristics. However, SPICE provides an output-file indicating that a transistor is in strong inversion but the DCOP can be in the limit, and it can switch to a different condition. In this manner, we highlight the application of PSO and MOL to size operational transconductance amplifiers (OTAs), which DCOP conditions are improved by the introduction of a procedure that handles constraints to ensure that the transistors are in the appropriate DCOP. The Miller and RFC-OTA are the cases of study, and their sizing is performed using UMC 180 nm CMOS technology. In both OTAs, the objective function is the maximization of the gain-bandwidth product under the main constraint of guaranteeing DCOPs to improve two figures of merit and to provide robustness to Monte Carlo simulations and PVT variations.

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Section: Problem Formulation and Handling Of Constraintsmentioning

confidence: 99%

Section: Sizing Otas By Pso and Mol To Improve Dcop Conditionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

2020

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“…where x pbesti is the best personal position of a given particle, x Gbesti refers to the best position reached by the particle's neighbourhood, w is the inertia weight which takes typical values lower than 1; the acceleration factors c 1 and c 2 are positive learning factors, the r 1 and r 2 are random values uniformly sampled in between 0 and 1 for each dimension. For each particle, particle's position and velocity can be updated according to (9) and (10). This procedure is repeated until the maximum iterations reached.…”

Section: Optimisation Of Vco Through Psomentioning

confidence: 99%

“…Also, the optimisation of nano-CMOS devices and circuits is currently of great interest among the designers. Various multi-objective evolutionary algorithms [7][8][9][10] have been used for optimisation. Employment of multi-objective fast design methods such as polynomial regression and genetic algorithms is applied to the design of a nano-CMOS VCO.…”

Section: Introductionmentioning

confidence: 99%

Performance enhancement of a VCO using symbolic modelling and optimisation

Panda

Patnaik

Mal

2018

IET Circuits, Devices & Systems

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This study proposed an application of symbolic technique on the characterisation of a ring voltage controlled oscillator (VCO) for optimum performance. Here nullor-based symbolic noise modelling and analysis of the CMOS ring VCO is carried out. Circuit equations are processed through modelling of all the metal-oxide-semiconductor field-effect transistors with their nullor equivalent. The closed-form expressions for the total output noise density and phase noise of VCO are obtained. With this technique, the total output noise density and phase noise calculated are compared with the results obtained from the transistorlevel simulation. From the comparison, it has been observed that the nullor-based modelling and analysis simplifies the noise expression as well as reduces CPU execution time. The performance enhancement of the VCO is carried out using two different optimisation techniques. These are particle swam optimisation and non-dominated sorting genetic algorithm. The results obtained for the optimised VCO are then tested using SPICE. The SPICE result shows a significant improvement in phase noise, power consumption and tuning range for the optimised VCO.

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