Size confinement effect in graphene grown on 6H-SiC (0 0 0 1) substrate

Mikoushkin, V. M.; Shnitov, V. V.; Лебедев, А. А.; Lebedev, S. P.; Nikonov, S.V.; Vilkov, O. Yu.; Iakimov, Tihomir; Yakimova, Rositsa

doi:10.1016/j.carbon.2015.01.015

Cited by 12 publications

(18 citation statements)

References 28 publications

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“…Contrary to the Schottky diodes, the potential barrier height (2.53 eV [23], 2.70 eV [61] and 2.90 eV [24]) in such structures can be as large as the band gap energy of silicon carbide (E g = 3.23 eV). There are possible explanations for these phenomena, which are connected with specific features of the graphenization of SiC, unusual polarization-induced p-type doping of the epitaxial graphene or even more likely the formation of the p-n junction between graphene and SiC.…”

Section: Observations Of Uncommon Phenomena At the Graphene/sic Intermentioning

confidence: 96%

Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface

et al. 2017

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Abstract:In spite of the great expectations for epitaxial graphene (EG) on silicon carbide (SiC) to be used as a next-generation high-performance component in high-power nano-and micro-electronics, there are still many technological challenges and fundamental problems that hinder the full potential of EG/SiC structures and that must be overcome. Among the existing problems, the quality of the graphene/SiC interface is one of the most critical factors that determines the electroactive behavior of this heterostructure. This paper reviews the relevant studies on the carrier transport through the graphene/SiC, discusses qualitatively the possibility of controllable tuning the potential barrier height at the heterointerface and analyses how the buffer layer formation affects the electronic properties of the combined EG/SiC system. The correlation between the sp 2 /sp 3 hybridization ratio at the interface and the barrier height is discussed. We expect that the barrier height modulation will allow realizing a monolithic electronic platform comprising different graphene interfaces including ohmic contact, Schottky contact, gate dielectric, the electrically-active counterpart in p-n junctions and quantum wells.

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Section: Observations Of Uncommon Phenomena At the Graphene/sic Intermentioning

confidence: 96%

Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface

et al. 2017

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“…The energy structure in the density of occupied states of graphene grown on n-type 6H-SiC(0001) has been study recently. As shown in Figure 26, a quantum well (QW) and quantum well levels can be created [129]. Photoelectron spectroscopy shows that the energy structure in the valence band close to the Fermi level is described by quantum well states (E1 = 0.3 eV, E2 = 1.2 eV, E3 = 2.6 eV).…”

Section: Growth Of Graphene On Si Facementioning

confidence: 99%

Epitaxial Graphene on SiC: A Review of Growth and Characterization

2016

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This review is devoted to one of the most promising two-dimensional (2D) materials, graphene. Graphene can be prepared by different methods and the one discussed here is fabricated by the thermal decomposition of SiC. The aim of the paper is to overview the fabrication aspects, growth mechanisms, and structural and electronic properties of graphene on SiC and the means of their assessment. Starting from historical aspects, it is shown that the most optimal conditions resulting in a large area of one ML graphene comprise high temperature and argon ambience, which allow better controllability and reproducibility of the graphene quality. Elemental intercalation as a means to overcome the problem of substrate influence on graphene carrier mobility has been described. The most common characterization techniques used are low-energy electron microscopy (LEEM), angle-resolved photoelectron spectroscopy (ARPES), Raman spectroscopy, atomic force microscopy (AFM) in different modes, Hall measurements, etc. The main results point to the applicability of graphene on SiC in quantum metrology, and the understanding of new physics and growth phenomena of 2D materials and devices.

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“…Kim et al [34] previously claimed the metallicity of this Sn-Si interface but the inferior quality of the buffer layer sample used with significant density of states at EF before intercalation depreciates their statement. Peaks at binding energies of about 0.3, 1.2 and 2.6 eV may originate from the quantum well states due to the potential relief of the valence bands at the interface [35]. After oxidation, the states around EF disappear which manifests a metal-dielectric transition in the system.…”

Section: Resultsmentioning

confidence: 99%

Metal-dielectric transition in Sn-intercalated graphene on SiC(0001)

2017

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The Sn intercalation into a buffer layer graphene grown on 4H-SiC(0001) substrate has been studied with spectroscopic photoemission and low energy electron microscope. Both SnSi x and SnOx interfacial layers are found to form below the buffer layer, converting it into a quasi-freestanding monolayer graphene. Combining the various operation modes of the microscope allows a detailed insight into the formation processes of the interlayers and their thermal stability. In particular, at the interface we observed a reversible transition from silicide to oxide after exposure to ambient pressure and subsequent annealing. This metal-dielectric transition might be useful for interface engineering in graphene-based devices.

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Size confinement effect in graphene grown on 6H-SiC (0 0 0 1) substrate

Cited by 12 publications

References 28 publications

Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface

Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface

Epitaxial Graphene on SiC: A Review of Growth and Characterization

Metal-dielectric transition in Sn-intercalated graphene on SiC(0001)

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