SIRC: An Extensible Reconfigurable Computing Communication API

Eguro, Ken

doi:10.1109/fccm.2010.29

Cited by 37 publications

(21 citation statements)

References 2 publications

(2 reference statements)

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“…To the best of our knowledge, there is no general purpose MATLAB based library to integrate the processing power and parallelism provided by FPGAs in higher level language such as MATLAB. Due to the complexity and complications involved in FPGA system design, designers usually employ easy to integrate platform such as NVIDIA GPUs with CUDA support to surpass CPU processing capability [8]. Also specialized ASICs (applicationspecific integrated circuits) are developed to achieve high performance in different application domains, but this did not prove to be a cost effective solution.…”

Section: Fpga-gpu-cpu Computing Platformmentioning

confidence: 99%

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FPGA Accelerated Computing Platform for MATLAB and C/C++

Rasul¹,

Mutaal²,

Saqib³

et al. 2013

2013 11th International Conference on Frontiers of Information Technology

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With latest advancements in architecture, reprogrammability and availability of abundant on-chip resources, FPGAs (Field Programmable Gate Array) are used as hardware accelerators to speedup computationally intensive tasks with inherent parallelism. However non-availability of standard MATLAB and C/C++ computation routines and communication interface for general purpose programming restricted researchers and developers from easily utilizing the parallel computational ability of FPGAs in MATLAB and C/C++. In this article we propose a proof of concept implementation for software-hardware co-design that can be used with MATLAB and C/C++ to share the burden of intensified computing with the FPGA.Typical applications which can be divided into multiple tasks to be executed in parallel can be easily transferred to FPGA by utilizing the proposed method. Some of the applications which can efficiently use this concept are image processing, video processing, data encryption and data compression. Results obtained by using our method and routines implemented in software and hardware provide 50% to 100% computational acceleration, as compared to routines running in software on MATLAB running on a computer. The design and concept can aid developers to use FPGAs in combination with higher level computational languages such as MATLAB and C/C++.

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Section: Fpga-gpu-cpu Computing Platformmentioning

confidence: 99%

“…We have used Xilinx ML507 board containing Virtex 5 'FXT' FPGA chip. The details of this design are presented in [8]. We have used SIRC Ethernet Data Transfer Controller in 16-bit data transfer mode.…”

Section: ) Ethernet Data Transfer Controllermentioning

confidence: 99%

FPGA Accelerated Computing Platform for MATLAB and C/C++

Rasul¹,

Mutaal²,

Saqib³

et al. 2013

2013 11th International Conference on Frontiers of Information Technology

View full text Add to dashboard Cite

show abstract

“…However, currently we have implemented both modules in a single FPGA (Xilinx Virtex 5: xc5vlx110t-2ff1136) to allow us to focus on the hardware/software interface and tool flow. Our implementation of the Server/Monitor circuit has two parts: (1) SIRC, the module that supports communication with PC through Ethernet [14], and (2) Analyzer, the module that implements the control for the Readback and allows the user to actually communicate with the DUT FPGA through the probe. The Analyzer supports writing batch commands from PC.…”

Section: Hardware Blocksmentioning

confidence: 99%

gNOSIS: A Board-Level Debugging and Verification Tool

Khan

Pittman

Forin

2010

2010 International Conference on Reconfigurable Computing and FPGAs

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It is notoriously hard to verify and debug the final, board-level implementation of FPGA designs. The task involves manual intervention and creativity, unpredictable time costs, and it is further complicated by side-effects of the monitoring circuits inserted into the Design Under Test (DUT). In this paper, we introduce gNOSIS, an automated tool for board-level debugging and verification of FPGA designs. gNOSIS uses the Capture/Readback features of the FPGA to checkpoint the entire state of the circuit with little or no modification to the DUT. The tool then correlates the design registers provided in the netlist with their state in the FPGA configuration memory, and with the expected state. If the states match, execution proceeds by restoring the state of the FPGA and continuing execution for a set number of cycles. When an error is encountered, the time and location of the error is reported and the last good checkpoint is used for further debugging. gNOSIS eliminates the manual labor and long wait times required by currently available tools (e.g. Chipscope), and provides greater visibility at a lower cost. More importantly, it provides the required infrastructure for more intelligent debugging techniques, such as those based on assertions or formal methods.

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“…The two IO controllers used for the DIALIGN application, with fully RTL interfaces, in "DIALIGN implemented with fully RTL based IO interfaces" section were the SIRC based Ethernet controller [23] and the corresponding Groundhog SATA controller [21]. Because the Ethernet controller makes use of only block-rams at its top level for data intake and delivery, it can be adapted to connect with the MicroBlaze LMB interface.…”

Section: Dialign Implemented With Software Io Interfacesmentioning

confidence: 99%

IO and data management for infrastructure as a service FPGA accelerators

Moorthy

Gopalakrishnan

2017

J Cloud Comp

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We describe the design of a non-operating-system based embedded system to automate the management, reordering, and movement of data produced by FPGA accelerators within data centre environments. In upcoming cloud computing environments, where FPGA acceleration may be leveraged via Infrastructure as a Service (IaaS), end users will no longer have full access to the underlying hardware resources. We envision a partially reconfigurable FPGA region that end-users can access for their custom acceleration needs, and a static "template" region offered by the data centre to manage all Input/Output (IO) data requirements to the FPGA. Thus our low-level software controlled system allows for standard DDR access to off-chip memory, as well as DMA movement of data to and from SATA based SSDs, and access to Ethernet stream links. Two use cases of FPGA accelerators are presented as experimental examples to demonstrate the area and performance costs of integrating our data-management system alongside such accelerators. Comparisons are also made to fully custom data management solutions implemented solely in RTL Verilog to determine the tradeoffs in using our system in regards to development time, area, and performance. We find that for a class of accelerators in which the physical data rate of an IO channel is the limiting bottleneck to accelerator throughput, our solution offers drastically reduced logic development time spent on data management without any associated performance losses in doing so. However, for a class of applications where the IO channel is not the bottle-neck, our solution trades off increased area usage to save on design times and to maintain acceptable system throughput in the face of degraded IO throughput.

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SIRC: An Extensible Reconfigurable Computing Communication API

Cited by 37 publications

References 2 publications

FPGA Accelerated Computing Platform for MATLAB and C/C++

FPGA Accelerated Computing Platform for MATLAB and C/C++

gNOSIS: A Board-Level Debugging and Verification Tool

IO and data management for infrastructure as a service FPGA accelerators

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