gNOSIS: A Board-Level Debugging and Verification Tool

Abstract

It is notoriously hard to verify and debug the final, board-level implementation of FPGA designs. The task involves manual intervention and creativity, unpredictable time costs, and it is further complicated by side-effects of the monitoring circuits inserted into the Design Under Test (DUT). In this paper, we introduce gNOSIS, an automated tool for board-level debugging and verification of FPGA designs. gNOSIS uses the Capture/Readback features of the FPGA to checkpoint the entire state of the circuit with little or no modification to the DUT. The tool then correlates the design registers provided in the netlist with their state in the FPGA configuration memory, and with the expected state. If the states match, execution proceeds by restoring the state of the FPGA and continuing execution for a set number of cycles. When an error is encountered, the time and location of the error is reported and the last good checkpoint is used for further debugging. gNOSIS eliminates the manual labor and long wait times required by currently available tools (e.g. Chipscope), and provides greater visibility at a lower cost. More importantly, it provides the required infrastructure for more intelligent debugging techniques, such as those based on assertions or formal methods.

IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection

“…2.27 ). Assertions enhance observability coverage, making it easier to spot the source of an error [ 26 ]. 4.…”

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs

“…Traditional checkpoint techniques are mainly software checkpoint that are implemented with dedicated commands issued by the operating system [11]- [13]. In contrast, hardware checkpoint is introduced in recent years which utilizes hardware features to save and restore the system state [14]- [20]. According to the implementation methods, hardware checkpoint can be further divided into two categories.…”

“…The second category of hardware checkpointing is bitstream readback [18]- [20], which utilizes the readback feature provided by FPGA vendors, such as Xilinx and Altera. By capturing the system state into bitstream first, and then read the bitstream back to retrieve the checkpoint at a given time.…”