SiP-test: Predicting delivery quality

Biewenga, A.; Jong, Frans de

doi:10.1109/test.2007.4437652

Cited by 3 publications

(3 citation statements)

References 4 publications

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“…Combining multiple devices in a package is a completely different process in comparison to SOC or PCB design. Packaging multiple dices in a SiP, each with their own defects, that also has a defective impact from its assembly process, leads to an overall defect level that is higher than that of the equivalent SOC or PCB design [1]. A number of discrete chips of the functional complexity packaged in SiP result in the testing issues with the inability to provide test access or test points for the growing number of internal signals which are not brought out to pads.…”

Section: Introductionmentioning

confidence: 99%

Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Zhao

Jiang

Liu

2014

2014 Joint IEEE International Symposium on the Applications of Ferroelectric, International Workshop on Acoustic Transduction M

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A SiP(System in Package) consists of multiple chips stacked and connected within a package. And SiP testing is a significant and growing problem owing to the limited accessibility and its particular test flow. It requires individual chip-level, interconnections test, post-packaging test and final system testing. This paper presents an overview of SiP test flow and the problem encountered by SiP test, and suggests its solution the IEEE 1500 Standard for Embedded Core Test (SECT). IEEE 1500 provides test access structure and mechanisms to implement the parallel scheduling test for hierarchical SiP .

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Section: Introductionmentioning

confidence: 99%

Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Zhao

Jiang

Liu

2014

2014 Joint IEEE International Symposium on the Applications of Ferroelectric, International Workshop on Acoustic Transduction M

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“…But at the same time, the disadvantages of SiP are increasing risks in reliability, manufacturability, and difficulty with test access [2]. Packaging multiple dice, each with their own defect level, in a SiP that also has a defect level from its assembly process, leads to an overall defect level that is higher than that of the equivalent SOC design [3].A number of discrete chips of the functional complexity packaged in SiP result in the testing issues with the inability to provide test access or test points for the growing number of internal signals which are not brought out to pads. Accordingly, SiP testing has a big challenge owing to the amount constraint of the pads and their physical access limitation.…”

Section: Introductionmentioning

confidence: 99%

“…Each of the components used in SiP will have had a certain amount of testing [3]. This paper presents a SiP microsystem and provides the final test process of the SiP microsystem with a test system which sets up specifically.…”

Section: Introductionmentioning

confidence: 99%

Research on testing of a microsystem based on SiP

Zhao

Jiang

Liu

2013

2013 14th International Conference on Electronic Packaging Technology

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System in Package (SiP) technology satisfies the further increasing demand by integration of different functions into one unit to reduce size and improve functionality. But the disadvantages of SiP are also increased risks in reliability, manufacturability, and difficulty with test access. A complete final test is necessary before its application. This paper presents a functional test scheme for a mircosystem based on 3D-SiP. Test system consists of a test board designed specifically and Cygwin environment of PC in debug support unit (DSU) and JTAG TAP techniques. It allows the complete final system-testing carry out in a fast, flexible, and nondestructive way. And it can improve the testability and reliability of microsystem.

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