Single-Slope Look-Ahead Ramp ADC for CMOS Image Sensors

Elmezayen, Mohamed R.; Wu, Bingxing; Ay, Suat U.

doi:10.1109/tcsi.2020.3007882

Cited by 19 publications

(10 citation statements)

References 26 publications

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“…An analog-to-digital converter (ADC) is indispensable in many implementations, such as COMS sensor imaging [ 1 ], liquid helium environment [ 2 ], positron emission tomography (PET) [ 3 ], and so on. More particularly, analog-to-digital converters (ADCs) and time-to-digital converters (TDCs) are usually used in PET equipment to estimate the energy and arrival time of electrical signals from silicon photomultiplier tube (SiPM) detectors.…”

Section: Introductionmentioning

confidence: 99%

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Zhang

Zhao

Chen

et al. 2022

Sensors

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A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

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Section: Introductionmentioning

confidence: 99%

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Zhang

Zhao

Chen

et al. 2022

Sensors

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“…A low-power ADC architecture is required for the sake of achieving a prolonged battery life for the implantable neural interfaces. To meet the requirements of low power consumption (below 25 µW), low sampling rate (below 100 ksamples/s), and resolution (8-10 b), several architectures are proposed in prior work, such as oversampling modulators [57], single-slope (SSR) or multiple-slope ramp (MSR) ADCs [58], and SAR-ADCs [52]. In this paper, the SAR-ADC architecture is designed due to its simpler architecture as well as meeting all the above criteria.…”

Section: Adc Architecturementioning

confidence: 99%

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Biswas

Mahbub

2021

Electronics

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This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

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“…If a metric is available for a row or full‐frame image complexity, it will be easy to gear up and down the biasing conditions in ASPs, or ADCs, or regulation efficiencies in on‐chip voltage regulators, or other parts of the readout chain could be tuned for optimum and uniform performance of the CIS. One such example is shown in Figure 1, where a multi‐mode ramp ADC [36] is used in a CIS with CPA, and full‐chip power consumption was measured from the imager in [36] at 20 frames per second for 1 min capturing the same scene images. Mode 1 is the standard ADC mode, where the ADC works normally without any speedup process, so it has the maximum power consumption as it works for the longest time.…”

Section: Conversion Complexity Metricmentioning

confidence: 99%

“…Measured full‐chip power consumption of a CIS with CPA and integrated ramp‐ADC in [36] for different modes. (a) Mode 1 for normal ADC operation.…”

Section: Conversion Complexity Metricmentioning

confidence: 99%

A new blind image conversion complexity metric for intelligent CMOS image sensors

Elmezayen

2020

IET Image Processing

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Many algorithms have been developed for complementary metal–oxide–semiconductor (CMOS) image sensors to speed up analogue‐to‐digital (A‐to‐D) conversion of captured images. However, there is no objective blind‐image quality metric available to compare and quantify the quality and effectiveness of these speed‐up algorithms. In this work, we developed a blind‐image quality and complexity metric for this purpose. The proposed metric relies on counting the successive zeros in a code histogram. The proposed metric is called the conversion complexity metric (CCM). The CCM is designed to quantify how complex, and to predict how much time and power consuming a captured image is for A‐to‐D conversion, mainly by integrating (ramp) type A‐to‐D converter used in column‐parallel architectures of a CMOS image sensor (CIS). The proposed metric, CCM, is tested for linearity, monotonicity, and sensitivity to many types of introduced distortion. The CCM is compared with other no‐reference and full‐reference image quality and complexity metrics. It accomplished, for brightness change distortion, 99% linearity and 316% sensitivity, providing a computationally efficient blind‐image quality metric that no other metrics provide for CIS to intelligently adjust and optimise on‐chip analogue and digital signal processing.

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Single-Slope Look-Ahead Ramp ADC for CMOS Image Sensors

Cited by 19 publications

References 26 publications

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

A new blind image conversion complexity metric for intelligent CMOS image sensors

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