Single-Event Upset (SEU) in a Dram with On-Chip Error Correction

Zoutendyk, J. A.; Schwartz, H. R.; Watson, Robert; Hasnain, Zille; Nevill, Leland R.

doi:10.1109/tns.1987.4337471

Cited by 19 publications

(7 citation statements)

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“…This relatively long "integration time" makes DRAMs vulnerable to upset from the integrated effects of multiple ions each depositing sub-critical amounts of charge. Ia addition, a single ion track can deposit charge onto multiple DRAM cells, resulting in multiple-bit upset from a single event [101][102][103][104][105]. TCDRAMs are also vulnerable to upset from ion shunts [98].…”

Section: Trenched-capacitor Dramsmentioning

confidence: 99%

Prevention of Single Event Upsets in Microelectronics

Hauser¹,

Weatherford²,

Kerns³

et al. 1991

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Section: Trenched-capacitor Dramsmentioning

confidence: 99%

Prevention of Single Event Upsets in Microelectronics

Hauser¹,

Weatherford²,

Kerns³

et al. 1991

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“…For example, using 256 Kbit DRAMS with an on-chip single-bit ECC and scrubbing the entire memory in 1.25 seconds, it was possible to scrub the effects of up to 5 particles /cm 2 /second. An on-chip ECC is not sufficient by itself, there were some events, such as pull down of whole bit lines, that affected many bits simultaneously and many of the single ion tracks affected multiple bits [32].…”

Section: Seu Fault Ratesmentioning

confidence: 99%

“…The present model is predicated on single digit faults resulting from ionizing radiation. However, an SEU is not necessarily a single upset; for instance, multiple bit faults occur due to single ionizing particles [5,32]. Another failure mode in highdensity memories which leads to multiple bit faults is alpha particle induced charge transfer between cells [10].…”

Section: Model Extensionsmentioning

confidence: 99%

“…a Single Event Upset (SEU), in computer memory or combinational logic circuits. SEU effects are found at sea level [24,31], in airborne avionics [19,20], and in space [1,2,5,7,10,12,14,23,24,25,26,27,28,32]. The effect of SEUs on chips has been extensively investigated and programs, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…Infrequent scrubbing leads to an accumulation of faults and increases the probability of exceeding the ECC's capability. Conversely, frequent scrubbing uses memory cycles that might otherwise be used by the operating system or an application program.There is a recognized tradeoff between using ECCs and scrubbing or using lower density, higher power, radiation-hardened semiconductors to achieve reliability [7,32]. Previous analyses of the tradeoffs between the use of simple ECCs, the additional hardware for the ECC, failure due to that additional hardware, and the system impact have been based on simplified analytical models; detailed analytical models are intractable.…”

mentioning

confidence: 99%

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System effects of single event upsets

Finn¹

1989

7th Computers in Aerospace Conference

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At the system level, SEUs in processors are controlled by fault-tolerance techniques such as replication and voting, watchdog processors, and tagged data schemes [13,16,30]. SEUs in memory subsystems are controlled by use of error control codes (ECCs) [4,17,21] and a process called scrubbing. The scrubbing process periodically reads each word in the memory. If the number of faulty digits in a word is less than or equal to the number the ECC can correct, then the digits are corrected and the word is written back to memory. If the number of faulty digits exceeds the ECC's capability, the errors cannot be corrected and the memory has failed. Fault-tolerance to memory failures requires either physical redundancy via replication or temporal redundancy via checkpoint rollback schemes. In most aerospace applications physical redundancy is undesirable because mass, volume, and power are at a premium.The rate at which SEUs are scrubbed from memory affects the performance and reliability of the entire computer system. Infrequent scrubbing leads to an accumulation of faults and increases the probability of exceeding the ECC's capability. Conversely, frequent scrubbing uses memory cycles that might otherwise be used by the operating system or an application program.There is a recognized tradeoff between using ECCs and scrubbing or using lower density, higher power, radiation-hardened semiconductors to achieve reliability [7,32]. Previous analyses of the tradeoffs between the use of simple ECCs, the additional hardware for the ECC, failure due to that additional hardware, and the system impact have been based on simplified analytical models; detailed analytical models are intractable.This paper introduces the idea of Markov modeling for SEU effects. Markov modeling allows extrapolation of chip failure rates to the subsystem and system level, allows more sophisticated tradeoff evaluations, and permits sensitivity analyses. The remainder of this paper is organized in three parts. Section 2 provides background about the SEU problem, expected SEU failure rates, and SEU control techniques. Section 3 introduces the use of Markov modeling techniques for memory subsystems and develops one model in detail. Section 4 presents the modeling results and generalizes the applicability of the modeling techniques.Single Event Upsets (SEUs) pose a serious threat to computer reliability and longevity. SEU effects are found at sea level, in airborne avionics, and in space. At the system level, SEUs in processors are controlled by replication and voting, watchdog processors, and tagged data schemes. SEUs in memory subsystems are controlled by periodically scrubbing words protected by an Error Control Code (ECC). The rate of memory scrubbing affects the performance and reliability of the entire computer system. There are tradeoffs between using radiation hardened semiconductors, scrubbing rates, and ECC capabilities. Previous tradeoff analyses have used simplified analytic models.The system effects of SEUs may be evaluated by Markov model...

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2011

Single Event Effects in Aerospace

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Single-Event Upset (SEU) in a Dram with On-Chip Error Correction

Cited by 19 publications

References 2 publications

Prevention of Single Event Upsets in Microelectronics

Prevention of Single Event Upsets in Microelectronics

System effects of single event upsets

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