Single Event Upset In CMOS Static Ram And Latches

Axness, Carl L.; Weaver, H. T.; Giddings, A. E.; Shafer, B.D.

doi:10.1109/nascod.1987.721132

[1987] NASECODE V: Proceedings of the Fifth International Conference on the Numerical Analysis of Semiconductor Devices and Int 1987

DOI: 10.1109/nascod.1987.721132

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Single Event Upset In CMOS Static Ram And Latches

Carl L. Axness¹,

H. T. Weaver²,

A. E. Giddings³

et al.

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Cited by 3 publications

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SEU characterization and design dependence of the SA3300 microprocessor

Sexton

Treece

Hass

et al. 1990

IEEE Trans. Nucl. Sci.

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The SEU vulnerability of the SA3300 16-bit microprocessor has been characterized, and the effects of two different design revisions on error rate have been explored. We found that the threshold for upset depends on the data pattern written into the general purpose registers. With all bits in the general purpose registers set to logic one, a design with 2-pm n-. and p-channel transistor lengths had a threshold LET of 35 MeVcm2/mg at 25°C and 4.5 volt operation. With all zero's stored in the registers the upset threshold increased by more than a factor of two to 83 MeVcm2/mg. A second design revision, with 1.25-pm and 1.75-pm n-and p-channel transistor lengths, respectively, was more vulnerable to upset, but exhibited a smaller dependence on logic state. Measured threshold LET was 23 and 35 MeVcm2/mg with all one's and all zero's, respectively. Microprobe measurements using a pulsed Nd:YAG laser suggest that the observed pattern dependence for both design revisions is due to bipolar photocurrent in a vertical n+pn transistor. A slight temperature dependence was observed in both design revisions. This is consistent with the use of oversized restoring transistors to minimize SEU vulnerability rather than polysilicon feedback resistors. More recent data show thresholds above 120 MeV-cmz/mg with 80 kn feedback resistors.

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SEU characterization and design dependence of the SA3300 microprocessor

Sexton

Treece

Hass

et al. 1990

IEEE Trans. Nucl. Sci.

Self Cite

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An Incremental Algorithm for Soft Error Rate Estimation of Combinational Circuits

Ghavami

Raji

Kiarash

et al. 2018

IEEE Trans. Device Mater. Relib.

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An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM

Weaver

Axness

McBrayer

et al. 1987

IEEE Trans. Nucl. Sci.

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Single Event Upset In CMOS Static Ram And Latches

Cited by 3 publications

References 5 publications

SEU characterization and design dependence of the SA3300 microprocessor

SEU characterization and design dependence of the SA3300 microprocessor

An Incremental Algorithm for Soft Error Rate Estimation of Combinational Circuits

An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM

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