Single event transients in deep submicron CMOS

Abstract-In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). In this paper, we propose two novel approaches to hardening integrated circuits against SEUs and SETs. The proposed approaches are fully-differential dual-interlocked storage cell (DICE) and triple path DICE (TPDICE).The fully-differential DICE and TPDICE approaches are compared against two existing approaches, which are triple modular redundancy (TMR) and basic SET-tolerant DICE. All approaches except for the basic SET-tolerant DICE scheme share a common theme, which is the ability to bypass SEUs and SETs. This is critical for performance, as it allows the system to proceed with subsequent operations while a cell is recovering from the effects of a particle strike. SET pulse widths can be substantial (up to 2 ns), and so high-performance systems cannot afford to pause operations while these pulses are present. The minimum clock periods obtained for the basic SET-tolerant approach were 515 ps with no SET, and 1310 ps with a 500 ps SET (in 0.18 m CMOS). In contrast, the clock periods for the bypass-capable approaches with no SET/500 ps SET were 628/749 ps for TMR, 348/480 ps for fully-differential DICE, and 434/552 ps for TPDICE. Among the approaches that bypass transient pulses, TPDICE is the most balanced. TMR suffers from overhead due to its need for external voting circuitry. In addition to this, fully-differential DICE cannot be used with combinational logic, while TPDICE can.

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“…Charge injected into combinational logic may initiate a voltage spike that propagates to memory [21]. This effect is known as an SET [22].…”

Section: Single-event Upsets and Single-event Transientsmentioning

confidence: 99%

Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

Blum

Delgado-Frias

2006

IEEE Trans. Nucl. Sci.

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“…Table I presents the SEU tolerance of four bitcells -the standard 6T, the DICE [15], the Quatro-10T [24], and the recently proposed SHIELD cell [23]. Assuming a natural space environment with a charge deposition of 1 pC [25], the results show that the DICE and SHIELD circuits are both suitable candidates, while the 6T and Quatro-10T cells do not provide sufficient immunity.…”

Section: Seu Immunity Comparisonmentioning

confidence: 99%

Single event upset mitigation in low power SRAM design

Atias

Teman

Fish

2014

2014 IEEE 28th Convention of Electrical &Amp; Electronics Engineers in Israel (IEEEI)

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Abstract-Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65 nm CMOS process under slightly scaled supply voltages.

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“…Since memories are particularly susceptible to SEU/SET events, these efforts were crucial to space and military applications. Yet other approaches address the modeling and simulation of radiation events [23], [24], [25]. Circuit hardening approaches can be classified as device level [8], circuit level [7], [10], [5], [15] and system level [19].…”

Section: Previous Workmentioning

confidence: 99%

A radiation tolerant Phase Locked Loop design for digital electronics

Kumar

Karkala

Garg

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this paper, we present a radiation hardened PLL design. Each of the components of this design -the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the loop filter are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our results demonstrate that over a large number of radiation strikes on a number of sensitive nodes in our design, the worst case jitter is just 18%. In the worst case, our PLL returns to the locked state in 16 cycles of the VCO clock, after a radiation strike.

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Single event transients in deep submicron CMOS

Cited by 41 publications

References 12 publications

Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

Single event upset mitigation in low power SRAM design

A radiation tolerant Phase Locked Loop design for digital electronics

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