Single Event Transient (SET) Mitigation Circuits With Immune Leaf Nodes

Sajjade, Faisal Mustafa; Goyal, Neeraj Kumar; Varaprasad, B.K.S.V.L.

doi:10.1109/tdmr.2021.3051846

Cited by 6 publications

(1 citation statement)

References 30 publications

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“…Transient faults are primarily caused by α-particle striking in integrated circuits and high energy radiations emitted by impurities in the material [19], [20]. The most common effect of transient faults in the NoC is bit flipping.…”

Section: Faults and Their Effect On Interconnection Links In Nocsmentioning

confidence: 99%

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

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Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

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Section: Faults and Their Effect On Interconnection Links In Nocsmentioning

confidence: 99%