Single Event Resilient Dynamic Logic Designs

Abstract

Dynamic logic families are commonly used in high speed applications, but they are susceptible to single event errors. This paper presents and evaluates three techniques of hardening dynamic logic-layout manipulation using charge sharing, addition of a feedback capacitor across the static inverter, and dual-rail domino logic with differential keepers. The layout-based design has better single event tolerance by sharing charge between NFET devices of the dynamic and static inverters; the design with a feedback capacitor makes the keeper more effective in recovering the hit node because of the increased propagation delay; the differential-keeper structure shows superior SET performance because the hit node could recover through the restoring path in the case of charge loss. These proposed designs along with the reference traditional keeper-based design were fabricated in a 130 nm technology node as shift register chains and then irradiated by heavy ion particles. Experimental results verified the mechanisms and effectiveness of these proposed designs.

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

“…The test system is described and illustrated elsewhere [24]. Briefly, in the system, the test chip is mounted onto a FPGA board through a DIMM socket.…”

“…One type of malfunctions induced by energetic particles in radiation environments is termed as soft errors and these errors can be recovered through recycling the power or rewriting the data [15,19,23]. Soft errors may occur in logic or storage circuits, and they are called Single Event Transient (SET) or Single Event Upset (SEU), respectively [8,22,24]. Figure 1 shows the typical structure of a 6 T SRAM bitcell, in which the core element is virtually a couple of back-to-back inverters with two access transistors.…”